SLIDE 1 Slides for Lecture 11
ENEL 353: Digital Circuits — Fall 2013 Term Steve Norman, PhD, PEng
Electrical & Computer Engineering Schulich School of Engineering University of Calgary
2 October, 2013
SLIDE 2 ENEL 353 F13 Section 02 Slides for Lecture 11
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Previous Lecture
◮ product-of-sums expressions ◮ product-of-sums canonical form ◮ axioms of Boolean algebra ◮ theorems of Boolean algebra from T1 and T1′ to
T10 and T10′
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Today’s Lecture
Theorems T11, T11′, T12, T12′. T12 and T12′ together are known as De Morgan’s Theorem, and are particularly useful in analyzing and designing digital logic. Using theorems to simplify equations. Going from logic equations to circuit designs. Related reading in Harris & Harris: Sections 2.3.3–2.3.5, 2.4
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T11 and T11′: Consensus Theorems
T11: (B · C) + (B · D) + (C · D) = (B · C) + (B · D) T11′, the dual of T11: (B + C) · (B + D) · (C + D) = (B + C) · (B + D) These allow dropping a redundant product from an SOP expression (T11) or redundant sum from an POS expression (T11′). Opportunities to use them are not easy to spot when doing algebraic manipulation, but it turns out that T11 justifies simplifications done using Karnaugh maps, as we’ll see a little later in the course.
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Do students need to memorize all the numbers and names for theorems?
For the most part, the answer is No. You will be tested on algebraic manipulation, but that is much more a matter of finding allowable steps in manipulations than it is a matter of knowing names of theorems. Example: You don’t need to know the names and numbers for theorems that allow you to do this . . . A = A · 1 = A(B + B) = AB + AB . . . but you must know that it is a valid and often useful step. A big exception: It is good to know exactly what is meant by De Morgan’s Theorem!
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T12 and T12′: De Morgan’s Theorem
Here are T12 and its dual, for N input variables: T12: B1 · B2 · . . . · BN = B1 + B2 + . . . + BN T12′: B1 + B2 + . . . + BN = B1 · B2 · . . . · BN For the cases of N = 2, N = 3, and N = 4, let’s write out De Morgan’s Theorem, using input variables A, B, C and D, as necessary.
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Mistakes you must avoid!
If you are doing algebraic manipulation just a little faster than you are thinking, you might do things like AB = ¯ A¯ B (Incorrect!)
A + B + C = A + B + C (Also incorrect!) What are correct transformations for AB and A + B + C?
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De Morgan’s Theorem, NAND gates and NOR gates
A NAND gate performs a “NOT-of-the-AND” function. De Morgan’s Theorem says that we can also view that as an “OR-of-the-NOTs” function. So the following two symbols both describe the behaviour of a single circuit element . . .
AB A B A B A + B = AB
Let’s write a similar description of a 3-input NOR gate and draw two different symbols for the gate.
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De Morgan’s Theorem and POS Canonical Form
Review . . . Goal Step 1 Step 2 SOP canonical form For truth table rows with F = 1, find true minterms. OR together minterms found in Step 1. POS canonical form For truth table rows with F = 0, find false maxterms. AND together maxterms found in Step 1. Suppose that the method for finding SOP canonical form makes sense to you, but the method for POS canonical form is a little mysterious. Let’s demonstrate how POS canonical form for F can be found starting with SOP canonical form for F.
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Using theorems to simplify expressions
A practical application of Boolean algebra theorems is to find an economical expression for a logic function. Usually, using fewer gates with smaller numbers of inputs per gate leads to circuits that
◮ use less chip area; ◮ consume less power; ◮ switch output faster when inputs change from 0 to 1 or
1 to 0. Example: Canonical SOP for the COUT function in a 1-bit full adder is ABCIN + ABCIN + ABCIN + ABCIN. Let’s use algebraic manipulation to find a simpler SOP expression for COUT(A,B,CIN).
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Using theorems to simplify expressions, continued
Using theorems to simplify expressions often works well, but it raises a few questions, such as . . .
◮ What is a good choice of theorem to use to make my
expression simpler?
◮ What is a bad choice, to be avoided, because it would
- nly make my expression more complicated?
◮ It’s so hard to avoid making mistakes that result in invalid
expressions! How the **** do I make sure things don’t go wrong?!?!
◮ How do I know when I’m done—how do I know there are
no more simplifications to be made? Unfortunately, these questions don’t always have simple
- answers. We’ll see later in the course that Karnaugh maps
help with answers to these questions, especially in the cases of 3–5 input variables.
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Schematics
A schematic is a diagram showing elements of a digital circuit along with the wires connecting the elements to each other and to overall inputs and
- utputs of the circuit. Usually the vital
power supply and ground connections to circuit elements are omitted to reduce clutter. The image at right shows some rules for drawing wires in schematics.
Image is Figure 2.24 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc.
wires connect at a T junction wires connect at a dot wires crossing without a dot do not connect
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Schematics: Examples
Expressions in SOP or POS form lead to easy-to-determine implementations of function with NOT, AND and OR gates. For the COUT function of a 1-bit full adder, let’s draw schematics for
◮ the canonical SOP expression; ◮ the simpler SOP expression we found a few slides back.
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Schematics: Guidelines for directions of information flow through circuit elements
Please follow these guidelines:
◮ Left-to-right flow of information through circuit elements
is best.
◮ Top-to-bottom flow through elements is second-best. ◮ Bottom-to-top flow through elements should be avoided if
possible but sometimes helps to keep schematics clear and compact.
◮ Right-to-left flow through elements is worst, but,
nevertheless, sometimes helps to keep schematics clear and compact.
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Next Lecture
Multilevel combinational logic. Unknown/illegal (X) and floating/high-impedance (Z) values in combinational logic. Related reading in Harris & Harris: Sections 2.5 and 2.6.
