Shallow Junctions & Contacts Prof. Krishna Saraswat - - PDF document

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Shallow Junctions & Contacts Prof. Krishna Saraswat - - PDF document

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Shallow Junctions & Contacts Prof. Krishna Saraswat Department of Electrical Engineering Stanford University Stanford, CA 94305 saraswat@stanford.edu Stanford University 1 Saraswat / EE311 / Shallow Junctions Outline

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  • Prof. Krishna Saraswat

Department of Electrical Engineering Stanford University Stanford, CA 94305 saraswat@stanford.edu

Shallow Junctions & Contacts

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Outline

  • Junction/contact scaling issues
  • Shallow junction technology
  • Ohmic contacts
  • Technology to form contacts
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MOS Device Scaling

N a

P N+ N+ L

x

  • x

X j

  • l
N a

P N+ N+ L

x
  • x
X j
  • l

Why do we scale MOS transistors? 1. Increase device packing density 2. Improve frequency response α 1/L 3. Improve current drive (transconductance gm) gm = ID V

G

VD = const W L µn K o x to x VD for VD < VDSAT , linear region W L µn K o x to x V

G VT

( )

for VD > VDSAT , saturation region

Why do we need to scale junction depth?

Constant E Field Scaling All device parameters are scaled by the same factor.

  • gate oxide thickness xox ↓
  • channel length L ↓
  • source/drain junction depth Xj ↓
  • Channel doping ↑
  • Supply voltage VDD ↓

Stanford University

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4 Q depleted by source Q depleted by drain

B B

N+ source N+ drain Gate P-Si

Depletion region L L rj

Short Channel Effects on Threshold voltage

  • L. Yau, Solid-State Electronics, vol. 17, pp. 1059, 1974

QB L = q N A W L + L' 2

  • L + L'

2L = 1 1+ 2 W rj 1

  • r j

L

Ddepletion width in a long channel device By trigonometry, we can write: We can approximate, the bulk charge as

VT = VFB 2 F QB Cox 1 1+ 2 W rj 1

  • rj

L

  • We can then approximate the threshold voltage as:

Threshold voltage is a function of junction depth, depletion width and channel length?

W = 2 (2 F +VBG ) qNA

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VT = VFB 2 F QB Cox 1 1+ 2 W rj 1

  • rj

L

  • Need for Shallow Source/Drain Junctions
  • Roll-off in threshold voltage as the channel length is reduced and

drain voltage is increased

  • To minimimize VT roll-off
  • Reduce as junction depth(rj)
  • Increase in Cox should increase gate control

Sheet resistance increases as junction depth is reduced

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  • Source/drain doping requirements show continuing drive to obtain

shallow junctions.

  • How will we form such shallow junctions?
  • How will we make low resistance contacts to them?
  • How will we minimize the sheet resistance of the junctions?

Year 1997 1999 2003 2006 2009 2012 Min Feature Size 0.25 0.18 0.13 0.10 0.07 0.05 Contact xj (nm) 100-200 70-140 50-100 40-80 15-30 10-20 xj at Channel (nm) 50-100 36-72 26-52 20-40 15-30 10-20

Source/drain Junction Depth

From the ITRS roadmap

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2000 2004 2008 2012 2016 10 20 30 40 50 60 70 SDE Junction Depth

  • Max. Ratio of Rsd to Ideal Rch

Physical Gate Length 2001 ITRS Gate Length or SDE Depth [nm]

Year

10 20 30 40 50 60

R

s d

/ R

c h

  • i

d e a l

[ % ]

  • As Lg scales down, Rsd becomes comparable to Rch
  • Rsd becomes important factor for device current
  • Parasitic portion of the device is now playing important role in

device performance and CMOS scaling

S/D Junction Scaling Trend

Ref: J. Woo (UCLA)

) (

th gs

  • x

ch ch

V V t L R

  • ⇒ Scaled with Lg

(Lch ↓, tox↓)

j sd sh sd

X N R R 1

  • ⇒ Difficult to scale

(Nsd const, Xj↓)

⇒ Rsd/Rch ↑

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Impact of Parasitic Series Resistance

Rcsd Rdp Rext Rov

x y = 0

Gate Sidewall Silicide

Next(x) Nov(y)

30 nm 50 nm 70 nm 100 nm 20 40 60 80 100 120 140 NMOS

Scaled by ITRS Roadmap

R

csd

R

dp

R

ext

R

  • v

Physical Gate Length Series Resistance (ohms)

Source: Jason Woo, UCLA

Problem in junction scaling:

  • Sheet resistance of a junction is a strong

function of doping density

  • Maximum doping density is limited by solid

solubility and it does not scale !

  • Silicidation can minimize the impact of

junction sheet resistance

  • Contact resistance Rcsd is one of the dominant

components for future technology 32 nm 53 nm 70 nm 100 nm 10 20 30 40 50 60 70

Rdp Rext Rov Rcsd

NMOS

Physical Gate Length Relative Contribution [%]

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32 nm 53 nm 70 nm 100 nm 10 20 30 40 50 60 70 Physical Gate Length

Rdp Rov Rext Rcsd

PMOS

Relative Contribution [%] 30 nm 50 nm 70 nm 100 nm 50 100 150 200 PMOS

Scaled by ITRS Roadmap

R

csd

R

dp

R

ext

R

  • v

Physical Gate Length Series Resistance (ohms)

  • Problem even more serious for PMOS
  • Rcsd will be a dominant component for highly scaled nanometer

transistor ( Rcsd/Rseries ↑ >> ~ 60 % for LG < 53 nm)

Relative Contributions of Resistance Components: PMOSFETs

Source: Jason Woo, UCLA Stanford University

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Outline

  • Junction/contact scaling issues
  • Shallow junction technology
  • Ohmic contacts
  • Technology to form contacts
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Dopant Diffusion

Gate Stack Anneal/Diffusion Ion Implant

  • Solutions to diffusion equations (Fick's laws) gives bulk diffusivity

Di = Di

  • e

_ EO kT

  • In shallow junction technologies, numerous effects alter these values

resulting in enhanced diffusion.

  • Transient enhanced diffusion
  • Diffusion affected by defects, e.g.,oxidation induced point defects

D = Di + Do e

_ t

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Oxidation increases interstitials (CI) and decreases vacancies (CV) from their equilibrium values. This in turn changes diffusivity.

Diffusion Affected by Oxidation Induced Point Defects

antimony boron

(Ref: Plummer, et al., Silicon VLSI Technology - Fundamentals, Practice and Models)

TSUPREM IV simulations of oxidation enhanced diffusion of boron (OED) and oxidation retarded diffusion of antimony (ORD) during the growth of a thermal oxide on the surface of silicon.

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DGB grain boundary diffusion DL lattice diffusion Generally DGB >> DL The worst-case demonstration of the defect enhanced diffusion of dopants is in polycrystalline silicon, which can be several times faster than diffusion in bulk Si because of defects at the grain boundaries.

Diffusion in Polycrystalline Materials

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Transient Enhanced Diffusion (TED)

Di = Di

  • exp E0

kT

  • D = Di + Do exp t
  • At lower temperatures, the damage can stay around longer and enhance the dopant

diffusion, while at higher temperatures the damage annihilates faster. Thus the diffusivity is a function of time during the transient. Where

40 keV, 10-14 cm-2 B 750ºC anneal

is intrinsic diffusity

Ref: Plummer, et.al.,

τ

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  • At lower temperature longer times are needed to anneal the damage
  • Transient enhanced dopant diffusion effects are stronger
  • Junction depth is larger
  • Higher temperature and shorter times are needed to minimize TED

Effect of TED on Junction Depth

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Boron Arsenic Depth

Concentration (cm-3)

Shallow Junction Formation Technologies Low Energy Implantation

40 keV As and B implants

Boron BF2 Depth Concentration (cm-3) 20 40 60 80 1016 1018 1020 1022 Depth (nm) 5 keV 1 keV as-implanted

As Concentration (cm-3)

12 keV B implants

  • Ref. Kasnavi, PhD Thesis

Stanford Univ. 2001

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Ion Implantation Damage

Heavy ions (As, P) Higher energy Light ions (B) Lower energy

  • Heavy ions (As, P) cause excessive damage turning implanted

region into amorphous

  • Light ions (B) have buried damage

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Ion Implantation Damage Anneal

  • Fully amorphized region can be fully annealed through solid phase regrowth
  • Buried damage leaves defects where damage was created as regrowth takes

place both from top and bottom. Heavy ions (As, P) Higher energy Light ions (B) Lower energy After implant After anneal Buried damage regrowth fully annealed Amorphous Crystalline SPE

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Pre-amorphization implants

10 sec 1000°C RTA Ge preamorphized Si preamorphized Not preamorphized Implanted

Depth (nm) Log concentration (cm-3)

Pre-amorphization implants can reduce the damage and yet get shallow junctions

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Solid Source Diffusion

Boron profiles after diffusion at 950°C of 50 nm COSi2 implanted with 5 X 1015 cm-2 BF2 (a) and (b)in Si after silicide removal.

In COSi2 In Si after silicide removal

Depth (nm) Depth (nm)

B C

  • n

c e n t r a t i

  • n

( c m

  • 3

)

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Gas Immersion Laser Doping (GILD)

Si wafer showing the adsorption of the dopant species onto the clean silicon surface. The dopant is incorporated into a very shallow region upon exposure to the excimer laser pulse.

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Junction Depth Vs. Sheet Resistance Tradeoff

250 500 750 1000 10 20 30 40 50 60 Rs (/ ) Y=2000, L g=180nm 2002, 130nm Roadmap 2011, 50nm 2014, 35nm 2008, 70nm 2005, 100nm 1 keV limit 5 keV limit

1020C spike

Junction Depth (nm)

  • Ref. Kasnavi, PhD Thesis Stanford Univ. 2001

It will be difficult to meet the ITRS scaling requirments of junction depth and sheet resistance

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Solutions to Shallow Junction Resistance Problem

Extension implants Elevated source/ drain Silicidation Schottky Source/Drain

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Effect of Scaling of Contacts and Junctions

Silicidation of junctions is necessary to minimize the impact of junction parasitic resistance

Ref: Ohguro, et al., ULSI Science and Technology 1997, Electrochemical Soc. Proc., Vol. 97-3

R (total) = Rch + Rparasitic Rparasitic = Rextension + Rextrinsic Rextension = Rd’ + Rs’ Rextrinsic = Rd + Rs + 2Rc

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Elevated S/D Technology

  • Elevated S/D structure ⇒ Reduction of Rcsd by increasing Nif &

reducing Rsh,dp underneath silicide

From A. Hokazono et al (Toshiba), IEDM2000

  • =

T con T c csd

L L L R coth

  • dp

sh c

R LT

,

  • =
  • if

b c

N q

  • exp

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New Structures and Materials for Nanoscale MOSFETs

(From Handout #1)

  • 1. Electrostatics - Double Gate
  • Retain gate control over channel
  • Minimize OFF-state drain-source

leakage

  • 2. Transport - High Mobility Channel
  • High mobility/injection velocity
  • High drive current for low intrinsic

delay

  • 3. Parasitics - Schottky S/D
  • Reduced extrinsic resistance
  • 4. Gate leakage - High-K dielectrics
  • Reduced power consumption
  • 5. Gate depletion - Metal gate

1 2 3

G G Si S D

Si

SiO2 C

BULK SOI Double gate

Bottom Gate

Top Gate

Source Drain High µ channel High-K

4 5

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  • Extrinsic resistance reduces gate overdrive ⇒ performance limiter in ballistic FETs
  • Ideally need very low specific contact resistivity and hyperabrupt lateral junctions
  • For a given doping abruptness:

–Too much underlap ⇒ dopants spill into channel ⇒ worse SCE –Too little underlap ⇒ large series resistance in extension tip

  • Extrinsic (S/D) resistance may limit performance in future ultrathin body DGFETs

Effect of Extrinsic Resistance on Double Gate MOSFETs

Shenoy and Saraswat, IEEE Trans. Nanotechnology, Dec. 2003

I Id

d = K

= K⋅ ⋅( (V Vg

g–

–V Vth

th–

–I Id

dR

Rs

s)

)α

α

1.E+13 1.E+14 1.E+15 1.E+16 1.E+17 1.E+18 1.E+19 1.E+20 1.E+21

40 45 50 55 60 65

x (nm) Net Doping (cm-3)

5nm/dec 4nm/dec 3nm/dec 2nm/dec 1nm/dec 0.5nm/dec

GATE Doping gradient

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Two Two kin kinds ds of

  • f tran

transistors sistors

Junction S/D MOSFET Schottky S/D MOSFET

Possible advantages

  • Better utilization of the metal/semiconductor interface
  • Possible option to overcome the higher parasitic resistance
  • Modulation of the source barrier by the gate
  • High Vg ⇒ barrier thin ⇒ tunneling current ⇑ ⇒ ION ⇑
  • Low Vg ⇒ barrier thick ⇒ tunneling current ⇓ ⇒ IOFF ⇓
  • Better immunity from short channel effects

Possible Disadvantage

  • Tradeoff between short channel effect vs. ION reduction due to the Schottky barrier
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Schottky Barrier Source/Drain SOI MOSFET

Lg + Spacers =27nm Tilted Source ErSi2 Gate N+poly, ErSi2 W=25nm

PtSi PMOS 20 nm 4 nm 1.2 V 270 uA/um 100 mV/dec 5E5

  • 0.7 V

ErSi NMOS 15 nm 4 nm 1.2 V 190 uA/um 150 mV/dec 1E4

  • 0.1 V

Lg Tox Vg-Vt Ion Swing Ion/Ioff Vt

  • 1.5
  • 1.0
  • 0.5

0.0 0.5 1.0 1.5 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 NMOS Tox = 4nm Lg = 15nm PMOS Tox = 4nm Lg = 20nm |Vsd| from 0.2V to 1.4V in steps of 0.4V |Id| (A/µ m) Vg (V)

  • J. Boker et al.- UC Berkeley

Lg~20 nm FETs with Complementary Silicides PtSi PMOS, ErSi NMOS

  • Metal S/D reduce extrinsic resistance
  • But Schottky barrier reduces Ion
  • Need low barrier technology to ensure high Ion

BOX

Si Silicide Gate

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Doped vs. Schottky S/D DG Device Comparison Simulations

 Low barrier height metal contact required to achieve high I

high ION

ON and low

and low CV/I delay CV/I delay

 Extensive research needed to develop a

Extensive research needed to develop a low barrier technology

ION vs. IOFF CV/I Delay

Source: King/Bokor,U.C. Berkeley Ref: R. Shenoy, PhD Thesis, Stanford 2004

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Outline

  • Junction/contact scaling issues
  • Shallow junction technology
  • Ohmic contacts
  • Need to understand the physics of contacts

resistance and develop technology to minmize it

  • Technology to form contacts

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Conduction Mechanisms for Metal/Semiconductor Contacts

Contact resistance strongly depends on barrier height (φB) and doping density

Ef V I Ohmic Schottky (c) Field emission. (a) Thermionic emission (b) Thermionic-field emission Low doping Medium doping Heavy doping φB

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Specific Contact Resistivity (ρc)

V V n+

V = Vbulk + 2Vcontact = I (Rbulk + 2Rcontact)

For a uniform current density Rcontact = dVcontact dI = c A Rbulk = dVbulk dI = l A

  • Specific contact resistivity and not contact resistance is the fundamental

parameter characterizing a contact

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Tunneling - Ohmic Contacts

Fs F m Jsm

Xd = 2 K o i q Nd When Xd ≤ 2.5 – 5 nm, electrons can “tunnel” through the barrier. Required doping is: N dmin 2 K o i q Xd

2

6.2 1019cm3 for Xd = 2.5 nm Jsm = A*T k Fs

  • P(E)(1 Fm )dE

P(E) ~ exp - 2B h sm* N

  • Jsm exp 2xd

2m* qB qV

( )/h2

[ ]

c = coexp 2B h sm* N

  • hm cm 2

Net semiconductor to metal current is P(E) is the tunneling probability given by Current can be shown to be Specific contact resistivity is of the form

ρc primarily depends upon

  • the metal-semiconductor work function, φΒ,
  • doping density, N, in the semiconductor and
  • the effective mass of the carrier, m*.
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Specific contact resistivity

Specific Contact Resistivity to P-type Si

(S. Swirhun, PhD Thesis, Stanford Univ. 1987)

c = co exp 2 B qh sm* N

  • hm cm2

P-type Si Specific contact resistivity, ρc ↓

  • As doping density N↑
  • Barrier height φB ↓

Specific contact resistivity (Ωcm2) NA (cm-3)

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Specific Contact Resistivity to N-type Dopants

(S. Swirhun, PhD Thesis, Stanford Univ. 1987)

  • Similar trends for N-type Si
  • For a given doping density contact resistance

is higher for n-type Si than p-type.

  • This can be attributed to the barrier height
  • φBn > φBp

Specific contact resistivity (Ωcm2) ND (cm-3)

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Solid Solubility of Dopants in Silicon

  • Problem is worse for p-type dopants (B), solid solubility is lower
  • Maximum concentration of dopants is limited by solid solubility

PROBLEM: Solid solubility of dopants does not scale !

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Barrier Height of Metals and Silicides to Si

Ideal Schottky model Practical barrier with Fermi level pinning

φBN + φBP = Eg Φm < χ Φm > χ

. (Ref: S. Swirhun, PhD Thesis, Stanford Univ. 1987)

Barrier height to n- and p-type Si

(φBN hollow symbols and φBP solid symbols)

φBN ⇒ 2Eg/3 φBP ⇒ Eg/3

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Strategy for Series Resistance Scaling

60 120 180 240 300

R

csd

R

dp

R

ext

R

  • v

Source/Drain Engineering

Box Profile Low-Barrier Silicide (ΦB = 0.2 eV) Box Profile Midgap Silicide Graded Junction Midgap Silicide LG = 53 nm

S/D Series Resistance [Ωµm]

Source: Jason Woo, UCLA Stanford University

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Potential Solutions for S/D Engineering

  • Rdp & Rcsd Scaling (ρc ↓)

⇒ Maximize Nif ( Rsh,dp ↓):

  • Laser annealing
  • Elevated S/D

⇒ Minimize ΦB:

  • Dual low-barrier silicide

(ErSi (PtSi2) for N(P)MOS)

  • Rov & Rext Scaling

⇒ Dopant Profile Control: ultra-shallow highly-doped box-shaped SDE profile (e.g., laser annealing, PAI + Laser Annealing)

Rcsd Rdp Rext Rov

x y = 0

Gate Sidewall Silicide

Next(x) Nov(y)

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Bandgap Engineering

  • Si1-xGex S/D & germanosilicide contact

− Assuming metal Fermi level is pinned near midgap − Similar barrier heights on n- or p-type material − Smaller bandgap for Si1-xGex − Reduction of Rcsd with single contact metal

From M. C. Ozturk et al. (NCSU), IEDM2002

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Energy band diagram and charging character of interface states for the metal-dielectric interface

  • Ideal Schottky model: when a metal and

a semiconductor or a dielectric form an interface, there is no charge transfer across the interface

  • A semiconductor or dielectric surface has

gap states due to the broken surface

  • bonds. These are spread across the

energy gap.

  • The wave functions of electrons in the

metal tail or decay into the semiconductor in the energy range where the conduction band of the metal

  • verlaps the semiconductor band gap.

These resulting states in the forbidden gap are known as metal-induced gap states (MIGS) or simply intrinsic states.

  • The energy level in the band gap at

which the dominant character of the interface states changes from donorlike to acceptorlike is called the charge neutrality level ECNL

Yeo, King, and Hu, J. Appl. Phys., 15 Dec. 2002

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Fermi Level Pinning

  • The metal work function is pinned near the charge neutrality level.
  • The charge neutrality level is defined as the energy level at which the

character of the interface states changes from donor-like to acceptor-like.

  • The charge neutrality level is situated at around one-third of the band gap in

the case of silicon ⇒ φbn = 2Eg/3 and φbp = Eg/3 Energy band structure of the Schottky contact and the electron energy dependence of the charging character of the metal semiconductor interface states.

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Fermi-level de-pinning

  • Can we alter the charge neutrality level? It may be possible to do so by

passivating the interface states. This can be done by modifying the interface. An issue of current research.

  • An example is selenium passivation of Si/Mg interface

the reconstructed Si [001] surface Band diagram of Mg–Si contacts (a) without interface states and (b) with interface states. I –V characteristics of Mg contacts to Si

  • M. Tao et al., APL, 2003

Se-passivated Si [001] surface

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Contact Resistance: 3D Model

  • Current flow in a contact is highly

non-uniform

  • Contact resistance does not scale

with area Silicon Contact Metal I Current I I I Silicide

J = Jx x + J y y + Jz z = 0 J = E = v V = 0 Majority carrier continuity equation outside the contact is Current density in the semiconductor is Combining these two equations we obtain

Itot = J dA

  • Total current over the contact area is

Solution of the above equations gives information about contact resistance. However, calculations are very involved. Stanford University

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Transmission Line Contact Model

I(x) = I1exp x c Rs

  • =

I1 exp x lt

( )

lt = c Rs

lt is the characteristic length of the transmission line - the distance at which 63%

  • f the current has transferred into the metal.

A simplified 1D solution of the contacts is

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Measurement of Contact Resistance and Specific Contact Resistivity (ρc)

R f c wd

For a very large value of lt or for d << lt

  • Rf gives reasonable assessment of the source/drain contact resistance

including the resistance of the semiconductor under the contact

  • Specific contact resistivity, ρc, can be calculated by measuring I, Vf or Ve
  • Measurement of Rf or Re is not straightforward and needs specialized test

structures

Re = Ve /I = Rsc wsinh d /lt

( )

Rf = Vf /I = Rsc w coth d /lt

( )

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Test Structure to Measure Contact Resistance: Transmission Line Tap Resistor

V24 = Vf + IRSi + Vf Rt = V24 I = 2Rf + Rsls w Rf = Vf / I1 = Rsc w coth d /lt

( )

is a very small number

Rf

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Test Structure to Measure Contact Resistance: Cross-bridge Kelvin Structure

N+ Diffusion Vk Rk = Vk I = V

14

I23 = c l2

l l

. .

I

Metal

.

l l

N+ Diffusion Metal Contact 1 2 3 4

Cross-bridge Kelvin structure used to measure an average contact resistance, called RK in the figure

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  • Specific contact resistivity (ρc) is a fundamental property of the

interface and should be independent of contact area

  • 1-D models overestimate the contact resistance (Rc)
  • 2-D models give more accurate results and should be used

Error in Specific Contact Resistivity due to 1-D Modeling

1-D model 2-D model Specific contact resistivity (ρc) Contact resistance

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Outline

  • Junction/contact scaling issues
  • Shallow junction technology
  • Ohmic contacts
  • Technology to form contacts

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Aluminum Contacts to Si

Oxide Silicon Aluminum N+ Oxide

  • Silicon has high solubility in Al ~ 0.5% at 450ºC
  • Silicon has high diffusivity in Al
  • Si diffuses into Al. Voids form in Si which fill

with Al: “Spiking” occurs.

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SLIDE 27

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Al/Si Alloy Contacts to Si

Al-Si phase diagram

By adding 1-2% Si in Al to satisfy solubility requirement junction spiking is minimmized But Si precipitation can occur when cool down to room temperature ⇒ bad contacts to N+ Si

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Silicide Contacts

  • Silicides like PtSi, TiSi2 make excellent contacts to Si
  • However, they react with Al
  • A barrier like TiN or TiW prevents this reaction

Oxide Silicon Aluminum N+ Oxide TiN TiSi2 PtSi TiW Barrier Contact

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SLIDE 28

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Silicide Contacts

Similar methods are used for other silicides

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Interfacial reactions

Integrity of ohmic contacts due to a physical barrier between Al and silicide

ΦB (eV) T (°C)

Schottky barrier reduction due to Al reaction with PtSi

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SLIDE 29

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Barriers

  • Silicides react with Al at T < 400°C
  • A barrier like TiN or TiW prevents this reaction upto T > 500°C

Structure Failure Temperature (˚C) Failure Mechanism (Reaction products) Al/PtSi/Si 350 Compound formation (Al2Pt, Si) Al/TiSi2/Si 400 Diffusion (Al5Ti7Si12, Si at 550˚C) Al/NiSi/Si 400 Compound formation (Al3Ni, Si) Al/CoSi2/Si 400 Compound formation Al9Co2, Si) Al/Ti/PtSi/Si 450 Compound formation (Al3Ti) Al/Ti30W70/PtSi/Si 500 Diffusion (Al2Pt, Al12W at 500˚C) Al/TiN/TiSi2/Si 550 Compound formation (AlN, Al3Ti)

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Outline

  • Junction/contact scaling issues
  • Shallow junction technology
  • Ohmic contacts
  • Technology to form contacts