SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip - - PowerPoint PPT Presentation

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SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip - - PowerPoint PPT Presentation

May 10, 2023 192 likes •441 views

SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks A. Ejlali*, B. M. Al-Hashimi Electronics and Comp. Science * Computer Engineering Dept. University of Southampton Sharif University of Technology Southampton, UK

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SLIDE 1

SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks

  • A. Ejlali*, B. M. Al-Hashimi†

*Computer Engineering Dept.

Sharif University of Technology Tehran, Iran

†Electronics and Comp. Science

University of Southampton Southampton, UK

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SLIDE 2

2

Overview

  • Introduction

– Pipelined On-Chip Interconnects – Addressed Problem

  • Energy Recovery Circuits
  • Energy Recovery Pipelined Interconnects

– Proposed Designs

  • Experiments
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SLIDE 3

3

Pipelined On-Chip Interconnects

IN DFF A1 DFF A2 DFF A3 DFF A4 OUT

  • Increased throughput
  • Freedom in choosing arbitrary topologies

–Pipelining decouples the throughput from the interconnect length.

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SLIDE 4

4

Addressed Problem

  • Reliability of on-chip interconnects

– In DSM technologies, flip-flops are susceptible to SEUs.

  • Energy consumption of on-chip interconnects

– Up to 50% of the total on-chip energy – SEU tolerance and low energy are at odds.

  • In this work: Specialized energy recovery

designs to achieve both the above objectives at the same time

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SLIDE 5

5

Previous Works

1) Energy recovery techniques for long wires

  • Voss et al., 2000.
  • Lyuboslavsky et al., 2000.

These works have not considered:

  • reliability issues
  • pipelined interconnects

2) Traditional Energy Recovery Logic Styles

  • Eight-phase dual-rail logic
  • 2LAL

They are not suitable for pipelined on-chip interconnects.

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SLIDE 6

6

The Principle of Energy Recovery

  • Conventional CMOS gates (Constant voltage charging)

2

2 1

DD L Conv

V C E =

GND VDD TR Charge TF Discharge Clock Period

  • Energy recovery CMOS gates (Constant current charging)

2

) (

DD L RF L Cur Cons

V C T RC E =

−

VA CL Vin Vin

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SLIDE 7

7

Characteristics of Energy Recovery Circuits

  • The trapezoidal signals provide

– Operating power – Timing information (power-clocks)

  • Essentially pipelined sequential circuits
  • Multiphase trapezoidal power-clock signals
  • Reversible logic functions
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SLIDE 8

8

Energy Recovery Pipelined Interconnects

P0 P1 P2 P3 P0 P1

L Stage

C n C ⋅ + = 1 1

  • Constant current charging of the non-pipelined interconnect

2 DD L RF L pipelined non

V C T RC E =

−

  • Constant current charging of the pipelined interconnect

⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ⋅ + = + = ⇒ =

2 2

1 1 ) 1 ( ) (

DD L RF L Stage pipeline DD Stage RF Stage Stage

V C T RC n E n n E V C T RC E

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SLIDE 9

9

Energy Saving via Pipelining

  • Conventional pipelined interconnects:

– Depth of pipelining⇑ ⇒ Throughput⇑

  • Energy recovery pipelined interconnects:

– Depth of pipelining⇑ ⇒ Throughput⇑

  • TRF decreases

– Depth of pipelining⇑ ⇒ Energy consumption⇓

  • TRF remains unchanged
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SLIDE 10

10

Proposed Designs

  • ER

– Energy Recovery Pipelined Interconnects

  • Energy Saving: 50%
  • Reliability: Slightly less reliable than conventional pipelines
  • SHER

– SEU-Hardened and Energy Recovery Pipelined Interconnects

  • Energy Saving: 30%
  • Reliability: Considerably hardened against SEUs

Disadvantages of Traditional Energy Recovery Logic Styles

– Eight-phase dual-rail logic

  • 8 power-clock signals

– 2LAL

  • Floating nodes
  • Problems in DSM technologies

– SEU-Hardness has not been considered

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SLIDE 11

11

ER Buffer

  • Dual-rail logic
  • 4 power-clocks
  • Circuit parts:

– Transmission gates – Transistor stack

ER Buffer Ai-1 Ai-1 Ai Ai Ai+1 Ai+1 Pj-1 Pj-1 Pj Pj Ai-1 Pj-1 Ai-1 Ai Ai+1 Ai-1 Ai Ai Pj Ai-1 Ai Ai Pj-1 Ai Ai+1 VDD Pj Ai-1 Ai Ai-1

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SLIDE 12

12

Clamp Transistor Stack

  • Two consecutive buffers

A Pj-1 A B C A B B Pj Pj B C D B C C Pj+1

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SLIDE 13

13

ER Pipelined Interconnects

ER Buffer A1 A1 A3 A3 P1 P1 P2 P2 ER Buffer A2 A2 A4 A4 P2 P2 P3 P3 A3 A3 ER Buffer IN IN A2 A2 P0 P0 P1 P1

P0 P1 P2 P3 IN IN A1 A1 A2 A3 Time

1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 12

1 1 1

A detailed example in Pages 4 and 5 of the paper

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SLIDE 14

14

SEU-Hardness

ER Buffer A1 A1 A3 A3 P1 P1 P2 P2 ER Buffer A2 A2 A4 A4 P2 P2 P3 P3 A3 A3 ER Buffer IN IN A2 A2 P0 P0 P1 P1

P0 P1 P2 P3 IN IN A1 A1 A2 A3 Time

1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 12

Sensitive Hardened

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SLIDE 15

15

Voltage Inverse vs. Logical Inverse

P P A A ~A #2 Clock Period #1 #3 #4 #5

A ¯ = voltage inverse of A, ~A=logical inverse of A

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SLIDE 16

16

SHER Buffer

Ai-1 Pj-1 Ai-1 Ai Ai Pj Ai-1 Ai Ai Pj-1 VDD Pj Ai-1 Ai Pj-1 Pj Pj-1 VDD Pj Ai Ai-1

  • 1

Ai ~Ai ~Ai ~Ai-1 ~Ai ~Ai-1 ~Ai ~Ai ~Ai ~Ai-1 ~Ai

SHER Buffer Pj-1 Pj-1 Pj Pj Ai-1 Ai-1 ~Ai-1 ~Ai-1 Ai Ai ~Ai ~Ai

  • 4-rail logic
  • 4 power-clocks
  • Circuit parts:

– Transmission gates – Clamp transistor

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SLIDE 17

17

SHER Pipelined Interconnects

P0 P1 P2 P3 IN ~IN A1 A2 A3 Time

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

~IN IN ~A1 ~A2 ~A3

SHER Buffer A1 A1 P1 P1 P2 P2 SHER Buffer A2 A2 P2 P2 P3 P3 A3 A3 SHER Buffer IN IN P0 P0 P1 P1 ~IN ~IN ~A1 ~A1 ~A2 ~A2 ~A3 ~A3

A detailed example in Pages 6, 7 and 8 of the paper

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SLIDE 18

18

Experimental Evaluation

  • SPICE simulations

– 45nm PTM technology

  • Interconnect

– CL=1pF

  • About 5 millimeters long wire in 45nm technology

– Throughput = 0.1 Gbps

  • Estimating energy consumption

– A random bit string consisting of 120 bits

  • Estimating reliability against SEUs

– Faults were injected using current sources

T t Inj

e T t T Q t I

−

⋅ ⋅ ⋅ = π 2 ) (

Pj-1 VDD Pj Ai-1

  • 1

Ai ~Ai ~Ai ~Ai-1 ~Ai IInj

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SLIDE 19

19

Energy Consumption of Pipelined On-Chip Interconnects

Pipelining Scheme # of FFs or # of Buffers Average Power (uW) Energy consumption*(pJ) 3 FFs 11.90 14.28 4 FFs 12.14 14.57 5 FFs 12.42 14.91 12 BUFs 7.42 8.90 16 BUFs 6.36 7.63 20 BUFs 5.56 6.67 12 BUFs 11.22 13.47 16 BUFs 9.62 11.54 20 BUFs 8.41 10.09 SHER ER Conventional * The energy consumption when a bit string with 120 random bits is transmitted

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SLIDE 20

20

Results Obtained From the Fault Injection Experiments

Pipelining Scheme # of FFs or # of Buffers # of SEUs % of SEUs* 3 FFs 377 9.2 4 FFs 618 15.08 5 FFs 792 19.33 12 BUFs 502 12.26 16 BUFs 816 19.92 20 BUFs 844 20.61 12 BUFs 16 BUFs 20 BUFs 2 0.05 * 4096 faults (simulated particle strikes) were totally injected SHER ER Conventional

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SLIDE 21

21

Summary

  • We have proposed the use of energy recovery

techniques to construct low energy and reliable pipelined on-chip interconnects.

  • We have presented two energy recovery designs:

– ER

  • Energy Saving: 50%
  • Reliability: Slightly less reliable than conventional pipelines

– SHER

  • Energy Saving: 30%
  • Reliability: Considerably hardened against SEUs
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SLIDE 22

22

Future Works

  • Analyzing the use of frequency scaling:
  • Analyzing the throughput/energy trade-off

– Depth of pipelining⇑ ⇒ Throughput⇑

  • TRF decreases

– Depth of pipelining⇑ ⇒ Energy consumption⇓

  • TRF remains unchanged

2

) (

DD L RF L Cur Cons

V C T RC E =

−

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SLIDE 23

23

Thank You