Routability-Driven and Fence-Aware Legalization for Mixed-Cell-Height Circuits
Haocheng Li1, Wing Kai Chow2, Gengjie Chen1, Evangeline F. Y. Young1, Bei Yu1
1The Chinese University of Hong Kong 2Cadence Design System Inc. 1 / 17
Routability-Driven and Fence-Aware Legalization for - - PowerPoint PPT Presentation
Routability-Driven and Fence-Aware Legalization for Mixed-Cell-Height Circuits Haocheng Li 1 , Wing Kai Chow 2 , Gengjie Chen 1 , Evangeline F. Y. Young 1 , Bei Yu 1 1 The Chinese University of Hong Kong 2 Cadence Design System Inc. 1 / 17
1The Chinese University of Hong Kong 2Cadence Design System Inc. 1 / 17
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a[Lin, Hsu, and Chang 2011] b[Raghavan et al. 2016]
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Cell M1 Cell Pin M2 Cell Pin M1 Rail M2 Rail Pin Access Pin Short
H
i | + |yi − y′ i |, satisfying b:
a[Darav, Bustany, et al. 2017] b[Chow, Pui, and Young 2016] c[Darav, Kennings, et al. 2016]
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Legalization MGL
Max Displacement Optimization Bipartite Matching Fixed Row & Fixed Order Optimization Dual Min Cost Flow
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f i j g k e c a b d h blockage f g e i c
4 3 2 1 L R
3 2 4 6 5 1 1 2 3 4
𝑦𝑢
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0 1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 7 8
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0 1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 7 8
−2 2 4 a xt Disp. Type A −2 2 4 b xt Type B −2 2 4 a c xt Disp. Type C −2 2 4 d b xt Type D
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xi,x−
i ,x+ i
i − x+ i )
i ≤ xi − x′ i ≤ x+ i ,
i ≤ 0 ≤ x+ i ,
i , ˜
i } of {xi, x− i , x+ i } are
i = x− i + ˜
i = x+ i + ˜
˜ xi,˜ x−
i ,˜
x+
i ,˜
x0
i − ˜
i )
i ≤ ˜
i ≤ ˜
i ,
i − ˜
i − ˜
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1 3 2 N P Z
2
1
2
1
3
3
3
3
3
1
2
2
1
2
1
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des_perf_1 des_perf_a_md1 des_perf_a_md2 des_perf_b_md1 des_perf_b_md2 edit_dist_1_md1 edit_dist_a_md2 edit_dist_a_md3 fft_2_md2 fft_a_md2 fft_a_md3 pci_bridge32_a_md1 pci_bridge32_a_md2 pci_bridge32_b_md1 pci_bridge32_b_md2 pci_bridge32_b_md3
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