Routability-driven Placement Algorithm for Analog Integrated - - PowerPoint PPT Presentation

Routability-driven Placement Algorithm for Analog Integrated Circuits

Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, and Soon-Jyh Chang

March 27, 2012 Department of Electrical Engineering National Cheng Kung University, Tainan, Taiwan

Outline Outline

 Introduction to Analog Placement  Routability-driven Analog Placement  Congestion Estimation  Placement Expansion  Proposed Placement Flow  Experimental Results  Conclusion

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Analog Placement Considerations Analog Placement Considerations

 Basic constraints

 Matching  interdigitated placement, common-centroid placement  Symmetry  symmetric placement  Proximity  adjacent placement

 Other considerations

 Thermal effects, stress gradients, etc.

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Interdigitated placement

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Common-centroid placement

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Symmetry constraint

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Proximity constraint Substrate Well

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Analog Placement Approaches Analog Placement Approaches

 Constructive method

 Generate placement according to schematic topology [Mehranfar,

JSSC’91] or signal paths [Long et al., ASP-DAC’06]

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VIP VIN M5 M1 M2 M4 M3 M8 M7 M6 CC1

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CC2 M9 M10 VB2

• VOP

VON

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M11 VIP VIN M5 M1 M2 M4 M3 M8 M7 M6 CC1

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CC2 M9 M10 VB2

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VON

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M11 M3 、 M4 M3 、 M4 M1 、 M2 M1 、 M2 M5 M5 M11 M11 M8 M8 M7、M10 M7、M10 M6 、 M9 M6 、 M9 CC1 and CC2 CC1 and CC2 M7 、 M10 M7 、 M10 M6 、 M9 M6 、 M9 W 2 W 2 W 2 W 2 W 2 W 2 W 2 W 2

Analog Placement Approaches Analog Placement Approaches

 Constructive method

 Generate placement according to schematic topology [Mehranfar,

JSSC’91] or signal paths [Long et al., ASP-DAC’06]

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Analog Placement Approaches Analog Placement Approaches

 Constructive method

 Generate placement according to schematic topology [Mehranfar,

JSSC’91] or signal paths [Long et al., ASP-DAC’06]

 Deterministic algorithm

 Enumerate all possible placements for the basic module sets,

and then combine these placements hierarchically [Strasser et al.,

ICCAD’08]

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Analog Placement Approaches Analog Placement Approaches

 Constructive method

 Generate placement according to schematic topology [Mehranfar,

JSSC’91] or signal paths [Long et al., ASP-DAC’06]

 Deterministic algorithm

 Enumerate all possible placements for the basic module sets,

and then combine these placements hierarchically [Strasser et al.,

ICCAD’08]

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Analog Placement Approaches Analog Placement Approaches

 Constructive method

 Generate placement according to schematic topology [Mehranfar,

JSSC’91] or signal paths [Long et al., ASP-DAC’06]

 Deterministic algorithm

 Enumerate all possible placements for the basic module sets,

and then combine these placements hierarchically [Strasser et al.,

ICCAD’08]

 Statistical algorithm

 Apply simulated annealing (SA) algorithm with floorplan

representations

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Representations for Analog Placement Representations for Analog Placement

 Topological representation is a popular method for modern VLSI design

 Smaller solution space (compared with absolute representation)  Need specific techniques to deal with placement constraints

 Previous work of handling symmetry constraint

 Sequence-pairs [Balasa & Lampaert, DAC’99]  O-trees [Pang et al., DAC’00]  Binary trees [Balasa, ICCAD’00]  TCG-S [Lin et al., ASP-DAC’05]  CBL [Liu et al., ASP-DAC’07]

 Previous work of tackling common-centroid constraint

 C-CBL [Ma et al., ICCAD’07]  B*-trees [Strasser et al., ICCAD’08]  Sequence-pairs [Xiao & Young, ASP-DAC’09]

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Routability-driven Analog Placement Routability-driven Analog Placement

 One of the objective function in SA algorithm is to minimize chip area, which makes blocks compact to the lower-left corner  For analog design, a compact placement is not practical  Routing over the active areas of analog devices is usually avoided to reduce parasitics and cross-talk effects  Reserve enough spaces between the devices for laying out wires

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Review of Congestion-aware Placement Review of Congestion-aware Placement

 Congestion-aware placement for analog circuits [Xiao et al., ICCAD’10]

 Whole placement region is divided into an nn mesh, and vertical

and horizontal congestions are estimated for each room

 Rooms are expanded column-by-column and row-by-row based on

the congestion map

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55 mesh Symmetry axis Non-symmetry module Symmetry group Symmetry axis Column expansion

Symmetry constraint is violated!

Symmetry constraint must be satisfied after placement expansion

Problem Formulation Problem Formulation

 Given a set of devices and topological placement constraints

 The active areas of all devices are considered as routing blockages  Routing congestion in the resulting placement P is minimized  All topological constraints are satisfied in the resulting placement P  Cost function (P):

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(P) =   AP +   WP +   CP AP: bounding-rectangle area of the placement WP: total wire length measured by half-perimeter estimation CP: estimation of routing congestion

Overview of Our Placement Flow Overview of Our Placement Flow

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Generate a compact placement based on ASF-B* -trees and HB* -trees Estimate routing congestion Expand congested regions Done Input devices, netlist, and topological placement constraints Minimum cost? No Yes

Congestion Estimation Congestion Estimation

 The way to predict congestion accurately is to use the same technique and parameters in both congestion estimation and global routing [Pan & Chu, ICCAD’06]

 Congestion-driven Steiner tree construction can be used for

congestion estimation and global routing

 Previous work: FastRoute [Pan & Chu, ICCAD’06], NTHU-Route

[Chang et al., ICCAD’08]

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Congestion map generation Congestion-driven Steiner tree construction Route two-pin nets using pattern routing and maze routing

• 1. Use FLUTE to generate the Steiner
• 1. minimal trees for all nets
• 2. Route two-pin nets using L-shaped
• 2. pattern routing
• 3. Generate congestion map from the
• 3. routing demand

Congestion Estimation Congestion Estimation

 The way to predict congestion accurately is to use the same technique and parameters in both congestion estimation and global routing [Pan & Chu, ICCAD’06]

 Congestion-driven Steiner tree construction can be used for

congestion estimation and global routing

 Previous work: FastRoute [Pan & Chu, ICCAD’06], NTHU-Route

[Chang et al., ICCAD’08]

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Congestion map generation Congestion-driven Steiner tree construction Route two-pin nets using pattern routing and maze routing

Reconstruct Steiner tree for each net according to the congestion map

Congestion Estimation Congestion Estimation

 The way to predict congestion accurately is to use the same technique and parameters in both congestion estimation and global routing [Pan & Chu, ICCAD’06]

 Congestion-driven Steiner tree construction can be used for

congestion estimation and global routing

 Previous work: FastRoute [Pan & Chu, ICCAD’06], NTHU-Route

[Chang et al., ICCAD’08]

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Congestion map generation Congestion-driven Steiner tree construction Route two-pin nets using pattern routing and maze routing

Reconstruct Steiner tree for each net according to the congestion map

Congestion Estimation Congestion Estimation

 The way to predict congestion accurately is to use the same technique and parameters in both congestion estimation and global routing [Pan & Chu, ICCAD’06]

 Congestion-driven Steiner tree construction can be used for

congestion estimation and global routing

 Previous work: FastRoute [Pan & Chu, ICCAD’06], NTHU-Route

[Chang et al., ICCAD’08]

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Congestion map generation Congestion-driven Steiner tree construction Route two-pin nets using pattern routing and maze routing

Reconstruct Steiner tree for each net according to the congestion map

Congestion Estimation Congestion Estimation

 The way to predict congestion accurately is to use the same technique and parameters in both congestion estimation and global routing [Pan & Chu, ICCAD’06]

 Congestion-driven Steiner tree construction can be used for

congestion estimation and global routing

 Previous work: FastRoute [Pan & Chu, ICCAD’06], NTHU-Route

[Chang et al., ICCAD’08]

 Proposed congestion map generation:

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Congestion map generation Congestion-driven Steiner tree construction Route two-pin nets using L-shaped pattern routing Generate congestion map from the routing demand

Congestion Map Generation with Analog Devices Congestion Map Generation with Analog Devices

 Grid graph model for global routing:  Since the active areas of all devices are considered as routing blockages, we reduce global edge capacities of a bin if the bin is

• ccupied by some devices

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Global edges Modules Global bins Grid graph model

Congestion Map Generation with Analog Devices Congestion Map Generation with Analog Devices

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Edge capacity: ce Routing demand: de ce1 , de1 ce2 , de2 ce1* , de1 ce2* , de2 a s ce1* = 0 if de > ce*, overflowe = de – ce*

• therwise overflowe = 0

a s ce2* = ce2 

Overview of Our Placement Flow Overview of Our Placement Flow

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Generate a compact placement based on ASF-B* -trees and HB* -trees Estimate routing congestion Expand congested regions Done Input devices, netlist, and topological placement constraints Minimum cost? No Yes

Placement Expansion Placement Expansion

 To eliminate routing overflow, we slightly expand congested regions of a compact placement

 Placement expansion for non-symmetry modules  Placement expansion for symmetry groups

 Dummy nodes are inserted into ASF-B*-trees or HB*-trees for placement expansion

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Review of ASF-B*-tree Review of ASF-B*-tree

 Concept of symmetry islands [Lin & Lin, DAC’07]

 Matching devices should be placed at proximity to reduce

mismatch [Pelgrom et al., JSSC’89]

 Each module should abut at least one of the other modules in the

same symmetry group

 A symmetry island defines a symmetric placement, in which

devices form a connected placement

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Symmetry group: S = { (M1 , M2) , (M3 , M4)}

Review of ASF-B*-tree Review of ASF-B*-tree

 Concept of symmetry islands [Lin & Lin, DAC’07]

 Matching devices should be placed at proximity to reduce

mismatch [Pelgrom et al., JSSC’89]

 Each module should abut at least one of the other modules in the

same symmetry group

 A symmetry island defines a symmetric placement, in which

devices form a connected placement

 Automatically symmetric-feasible B*-tree (ASF-B*-tree) is used to represent a symmetry island

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Review of HB*-tree Review of HB*-tree

 Hierarchical B*-tree (HB*-tree) deals with the placement of symmetry islands and non-symmetry modules  Hierarchy nodes can handle the groups which require matching, symmetry, and proximity constraints

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hierarchy node

Placement Expansion for Non-symmetry Modules Placement Expansion for Non-symmetry Modules

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b2 b1 b0 b2 b1 b0

Congested region Expansion width is determined according to congestion map

n0 n1 n2

B* -tree

n0 n1 n2

Placement Expansion for Non-symmetry Modules Placement Expansion for Non-symmetry Modules

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n0 n1 n2 n0 n1 n2 b2 b1 b0 b2 b1 b0 b2 b1 b0

Expansion height is determined according to congestion map

Placement Expansion for Non-symmetry Modules Placement Expansion for Non-symmetry Modules

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b0 b1' b2' b1 b2 b0 b1' b2' b1 b2 n0 nS0 n1

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Placement Expansion for Symmetry Groups Placement Expansion for Symmetry Groups

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Placement Expansion for Symmetry Groups Placement Expansion for Symmetry Groups

 ASF-B*-trees guarantee that each symmetry group remains symmetric after placement expansion

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Placement Expansion for Symmetry Groups Placement Expansion for Symmetry Groups

 ASF-B*-trees guarantee that each symmetry group remains symmetric after placement expansion

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Dummy node only needs to add half the expansion width

Outline Outline

 Introduction to Analog Placement  Routability-driven Analog Placement  Congestion Estimation  Placement Expansion  Proposed Placement Flow  Experimental Results  Conclusion

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Proposed Placement Flow Proposed Placement Flow

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Start Generate a placement P Cost calculation

1(P) =   AP +   WP

Minimu m cost? No Yes Candidate placement P* Input modules, nets, and constraints Stage 1 Stage 2 Cost calculation

2(P*) =   AP +   WP +   CP

Construct Steiner trees for all nets Estimate routing overflow Congestion elimination Minimu m cost? No Yes Over- congeste d? Yes No Perturbation for placement P* End

Proposed Placement Flow Proposed Placement Flow

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Cost calculation

2(P*) =   AP +   WP +   CP

Construct Steiner trees for all nets Estimate routing overflow Congestion elimination Minimu m cost? No Yes Over- congeste d? Yes No Perturbation for placement P* End Stage 2 Estimate routing overflow Over- congeste d? No Yes Expand all congested regions Reconstruct Steiner trees for all nets

Experimental Results Experimental Results

 Platform: 2.5GHz SUN Fire-X4250 workstation with 16GB RAM  Benchmark: two MCNC benchmark circuits

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Circuit # of mod. # of sym. mod.

• Mod. area (mm2)

ami33 33 7 (2+2+2+1) 1.16 = 100% ami49 49 5 (2+2+1) 35.45 = 100%

Experimental Results Experimental Results

 Platform: 2.5GHz SUN Fire-X4250 workstation with 16GB RAM  Benchmark: two MCNC benchmark circuits

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Circuit Without placement expansion With placement expansion Area (%) HPWL (mm) # of

• verflow

Time (sec.) Area (%) HPWL (mm) # of

• verflow

Time (sec.) ami33 107.11 37.38 154 103 113.25 47.73 556 ami49 108.44 569.25 253 206 115.32 677.24 1337 ami33 ami49

Experimental Results Experimental Results

 Platform: 2.5GHz SUN Fire-X4250 workstation with 16GB RAM  Benchmark: two MCNC benchmark circuits  Symmetry property is maintained after placement expansion

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ami33 ami49

Conclusion Conclusion

 Analog placement considering routability was introduced

 The active areas of all devices are considered as routing blockages  Routing congestion in the resulting placement is minimized  Symmetry constraint must be satisfied after placement expansion

 ASF-B*-trees were used for maintaining the symmetry property after placement expansion  Future work

 Consider symmetric routing during the congestion estimation

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Questions or Comments Questions or Comments

Thank you!

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