Pin Assignment Optimization for Multi2.5D FPGAbased Systems - - PowerPoint PPT Presentation

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Pin Assignment Optimization for Multi2.5D FPGAbased Systems - - PowerPoint PPT Presentation

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Pin Assignment Optimization for Multi2.5D FPGAbased Systems Outline Introduction Preliminaries Algorithm Experimental Results Conclusions 2 2018/3/28 CS,DEP. NTHU, TAIWAN Outline Introduction Preliminaries

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Pin Assignment Optimization for Multi‐2.5D FPGA‐based Systems

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Outline

  • Introduction
  • Preliminaries
  • Algorithm
  • Experimental Results
  • Conclusions

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Outline

  • Introduction
  • Preliminaries
  • Algorithm
  • Experimental Results
  • Conclusions

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Introduction

  • Multi‐FPGA systems are widely used for
  • Logic emulation
  • Rapid prototyping of large designs
  • Reconfigurable custom computing platforms

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Introduction

  • A multi‐FPGA system connected through
  • Direct hardwired connections
  • Programmable interconnection network
  • Consist of one or more FPICs
  • The available pin counts of the FPGAs limit the

utilization of FPGA logic resources in a mulit‐FPGA system.

  • Solution : time division‐multiplexing (TDM)

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Introduction

  • 2.5D FPGA

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Introduction

  • 2.5D FPGA

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Introduction

  • Interconnect resources between dies
  • the amount is less than that within a die
  • there is increased delay to cross the interposer

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Introduction

  • [6] : reducing the SLR crossings
  • routability
  • circuit speed
  • [6] focused on reducing the total SLR crossings by

SLR partitioning in a stand alone 2.5D FPGA.

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Introduction

  • The I/O signal counts per FPGA is

enormous.

  • I/O pin assignment can have a big impact
  • n the overall SLR crossings

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Outline

  • Introduction
  • Preliminaries
  • Algorithm
  • Experimental Results
  • Conclusions

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Preliminaries

  • multi‐FPGA system
  • multiplexed hardwired inter‐FPGA connections
  • 2.5D FPGAs

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Preliminaries

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Preliminaries

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Preliminaries

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Preliminaries

  • SLR partitioning and pin assignment results
  • f a FPGA are propagated to the FPGA P&R

tool

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SLR‐Aware Pin Assignment

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SLR‐Aware Pin Assignment

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SLR‐Aware Pin Assignment

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SLR‐Aware Pin Assignment

  • Given :
  • Set of 2‐pin inter‐FPGA subnets
  • TDM factors
  • Directions
  • which originate from the same net
  • Goal :
  • Assign all these 2‐pin subnets to physical wires and

pins to minimize the total SLR crossings subject to the constraints on the TDM factors and directions.

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Outline

  • Introduction
  • Preliminaries
  • Algorithm
  • Experimental Results
  • Conclusions

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Algorithm

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Initial Feasible Pin Assignment Generation

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TDM = 2 # = 101

Required physical wires = 101/2 = 51

TDM = 10 # = 5

Required physical wires = 5/10 = 1

26 15 10 1

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Pin Assignment Refinement

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Pin Assignment Refinement

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Pin Assignment Refinement

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Outline

  • Introduction
  • Preliminaries
  • Algorithm
  • Experimental Results
  • Conclusions

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Experimental Results

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Heuristic

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TDM = 20 # = 1001

Required physical wires = 1001/20 = 51

TDM = 10 # = 5

Required physical wires = 5/10 = 1

20 20 10 1 1

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Experimental Results

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Comparing our proposed algorithm against two other approaches.

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Experimental Results

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Execution statistics of our algorithm.

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Experimental Results

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Comparing 10 trials of our algorithm using different initial feasible pin assignments on each test case.

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Outline

  • Introduction
  • Preliminaries
  • Algorithm
  • Experimental Results
  • Conclusions

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Conclusions

  • We introduced the SLR‐aware pin assignment

problem for modern multi‐FPGA system utilizing high capacity 2.5D FPGAs.

  • We proposed an iterative improvement algorithm

based on integer linear programming to minimize the total number of SLR crossings in all FPGAs.

  • Experimental results showed that the amount of

SLR crossings can be significantly reduced by over 30% on average compared to two other approaches.

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Thank you.

Q & A

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