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Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Introduction to Structured VLSI Design ‐ VHDL IV

Joachim Rodrigues

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Overview

• Memories
• Strictly Structured VHDL

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Memories

• Abstraction levels

– Behavorial model (arrays) – Synthesizable model (registers) – Hard macros (technology dependent) Hard macros are technolgy dependent and require less area than registers.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Ram vs Register

RAM characteristics

– RAM cell designed at transistor level – Cell use minimal area – Is combinatorial and behaves like a latch – For mass storage – Requires a special interface logic

Register characteristics

– DFF (may) require much larger area – Synchronous – For small, fast storage – e.g., register file, fast FIFO

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

RAM‐Single Port

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY ram IS GENERIC ( ADDRESS_WIDTH : integer := 4; DATA_WIDTH : integer := 8 ); PORT ( clock : IN std_logic; data : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0); write_address, read_adress : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0); we : IN std_logic; q : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0) ); END ram; ARCHITECTURE rtl OF ram IS TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0); ram_block : RAM; BEGIN PROCESS (clock,we) BEGIN IF (clock'event AND clock = '1') THEN IF (we = '1') THEN ram_block(to_integer(unsigned(write_address))) <= data; END IF; q <= ram_block(to_integer(unsigned(read_address))); END IF; END PROCESS; END rtl;

A single word may be read or written during one clock cycle. an adress is always positiv

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

RAM‐dual port

USE work.ram_package.ALL; ENTITY ram_dual IS PORT (clock1, clock2 : IN std_logic; data : IN word; write_address, read_address : IN address_vector; we : IN std_logic; q : OUT word ); END ram_dual; ARCHITECTURE rtl OF ram_dual IS SIGNAL ram_block : RAM; SIGNAL read_address_reg : address_vector; BEGIN PROCESS (clock1) BEGIN IF (clock1'event AND clock1 = '1') THEN IF (we = '1') THEN ram_block(write_address) <= data; END IF; END IF; END PROCESS; PROCESS (clock2) BEGIN IF (clock2'event AND clock2 = '1') THEN q <= ram_block(read_address_reg); read_address_reg <= read_address; END IF; END PROCESS; END rtl;

Dual Port: Concurrent Read and Write Dual-port RAMs Are very expensive in area and should be avoided !! Dual port functionality may be realized by a hybrid single-port RAM. Read on pos edge and write

• n neg edge.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

ROM

library IEEE; use IEEE.std_logic_1164.all; entity rom_rtl is port (ADDR: in INTEGER range 0 to 15; DATA: out STD_LOGIC_VECTOR (3 downto 0)); end rom_rtl; architecture XILINX of rom_rtl is subtype ROM_WORD is STD_LOGIC_VECTOR (3 downto 0); type ROM_TABLE is array (0 to 15) of ROM_WORD; constant ROM: ROM_TABLE := ROM_TABLE'( ROM_WORD'("0000"), ROM_WORD'("0001"), ROM_WORD'("0010"), ... begin DATA <= ROM(ADDR); -- Read from the ROM end XILINX;

Behavioral 16x4 ROM model For a real hard macro (ASIC), a file that holds the coefficients need to submitted to the ASIC Vendor.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Register File

Registers are arranged as an 1‐d array

• Each register is accessible with an address
• Usually 1 write port (with write enable signal)
• May have multiple read ports

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Register File cont’d

4‐word register file w/ 1 write port and two read ports

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

• Register array:

– 4 registers – Each register has an enable signal

• Write decoding circuit:

– 0000 if wr_en is 0 – 1 bit asserted according to w_addr if wr_en is 1

• Read circuit:

– A mux for each read port

Register File cont’d

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

‐ GAISLER’S METHOD

Strictly Structured VHDL

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Strictly Structured VHDL

“Gaisler’s method” is a design methodology (code style), which can be summarized as: – Use records – Use synchronous reset – Apply strong hierarchies

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Strictly Structured VHDL

• How is it done?

– Local signals (r, rin) are stored in records and contain all registered values. – All outputs are stored in a entity specific record type declared in a global interface package – enables re‐use. – Use a local variable (v) of the same type as the registered values. – reset handling moves to combinational part.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Realization of FSMs‐ behavorial

architecture implementation of state_machine is type state_type is (st0, st1,st2, st3); -- defines the states type reg_type is record

• utput :

STD_LOGIC_VECTOR (m-1 downto 0); state : state_type; end record; Signal r ,rin : reg_type; begin combinational : process (input,reset,r) -- Combinational part variable v : reg_type; begin v : = r; -- Setting the variable case (r.state) is -- Current state and input dependent when st0 => if (input = ”01”) then v.state := st1; v.output := ”01” end if; when ... when others => v.state := st0; -- Default v.output := ”00”; end case; if (reset = ’1’) then -- Synchronous reset v.state := st0; -- Start in idle state end if; rin <= v; -- update values at register input

• utput <= v.output; -- Combinational output
• -output <= r.output; -- Registered output

end process;

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Realization of FSMs ‐ sequential

synchronous : process (clk)– This part is always, always the same begin if clk’event and clk = ’1’ then r <= rin; end if; end process; end architecture;

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Strictly Structured VHDL‐Advantages

Adding a signal in traditional style

• Add port in entity declaration
• Add signal to sensitivity list
• Add port in component declaration
• Add port in component instantiation

Adding a signal in Strictly Structured VHDL methodology

• Add element in record declaration

DUT DUT

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Structured VHDL

Obvious Advantages

• Readability
• Less written code
• Maintainance and re‐useability

Hidden Advantages

• Synthesizable
• Synchronous reset
• No need to update sensitivity lists
• Faster simulation (less concurrent statements)

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Structured VHDL‐Stored signals

Adding a stored signal in traditional style

• Add two signals (current, next)
• Add signal to sensitivity list
• Add reset value
• Update on clock edge

Adding a signal in Structured VHDL methodology

• Add element in declaration record

Comb Next Current Comb rin r

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Realization of FSMs ‐Example

architecture implementation of state_machine is type state_type is (st0, st1,st2, st3); -- defines the states type reg_type is record

• utput : STD_LOGIC_VECTOR (m-1 downto 0);

state : state_type; new_signal : std_logic; end record; Signal r ,rin : reg_type; begin combinational : process (input,reset,r) -- combinational part variable v : reg_type; begin v : = r; -- Setting the variable case (r.state) is -- Current state and input dependent when st0 => if (input = ’1’) then v.state := st1; v.output := ”01” end if; when ... when others => v.state := st0; -- Default v.output := ”00”; end case; Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Structured VHDL

library IEEE;use IEEE.STD_LOGIC_1164.all; library global_interface is input_type is record

• - Type record

newsignal : std_logic; end record; end; library IEEE; use IEEE.STD_LOGIC_1164.all; Use work.global_interface.pkg; entity state_machine is port (clk : in STD_LOGIC; reset : in STD_LOGIC; input : in input_type;

• utput :
• ut output_type;

end state_machine;

state_machine input_type

• utput_type

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Conclusions

Recommendations

– Use structured VHDL – Use synchronous reset – Use hierarchy (instantiation) extensively

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Configuration

• Testbench is reused by declaring a different configuration
• A configuration may realize different architectures, memories, etc.
• Examples:

– A synthesizable model / behavorial model – A synthesizable model / gate‐level model

Syntax:

configuration configuration_name of entity_name is for architecture_name for label|others|all: comp_name use entity [lib_name.]comp_entity_name(comp_arch_name) | use configuration [lib_name.]comp_configuration_name [generic map (...)] [port map (...)] ; end for; ... end for; end configuration_name;

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Configuration‐Example

configuration THREE of FULLADDER is for STRUCTURAL for INST_HA1, INST_HA2: HA use entity WORK.HALFADDER(CONCURRENT); end for; for INST_XOR: XOR use entity WORK.XOR2D1(CONCURRENT); end for; end for; end THREE;

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Non‐synthesizable VHDL

• The following VHDL keywords/constructs are ignored or rejected by most RTL

synthesis tools: – after, (transport and inertial) – wait for xx ns – File operations – generic parameters must have default values – All dynamically elaborated data structures – Floating point data types, e.g. Real – Initial values of signals and variables – Multiple drivers for a signal (unless tri‐stated) – The process sensitivity list is ignored – Configurations – Division (/) is only supported if the right operand is a constant power of 2

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

After Command

• <signal_name> <= value after <time>
• Example:

A <= ‘1’, ‘0’ after 100 ns, ‘1’ after 200 ns;

0 ns 100 ns 200 ns

Not synthesizable

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Wait Command

• Usage:

wait on <sensitivity list> wait until <expression> wait for <time interval>

• Examples :

process(a,b) begin sum <= a xor b after T_pd; carry <= a and b after T_pd; wait on a,b; end process; process (a,c) begin b <= a + c; wait for T_pd; end process; process(a) begin wait until (a=c) b<= not a; end process;

Not synthesizable

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Assertion Statement

To be used in the testbench

• Usage:

assert <expression> report <message> severity <Note | Warning | Error | Failure>;

• Example:

assert simulation(test_input_vector(i))=test_output_vector(i); report “Test vector failure”; severity failure;

Not synthesizable

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL IV

Watch out: Inferred Latches

Already mentioned: get rid of any Latches. Check the synthesis report and correct eventual case/if instructions