New Approaches to Harness Global Interconnects Jason Cong Computer - PowerPoint PPT Presentation

PART V New Approaches to Harness Global Interconnects Jason Cong Computer Science Department University of California at Los Angeles Email: cong@cs.ucla.edu Tel: 310-206-2775 http://cadlab.cs.ucla.edu/~cong ASPDAC'01 Tutorial Jason Cong 1

Part V Outline I Interconnect Interconnect- -Centric Design Flow Centric Design Flow I I Interconnect Performance Estimation Models Interconnect Performance Estimation Models I N IPEM for optimal IPEM for optimal wiresizing wiresizing N IPEM for IPEM for wiresizing wiresizing and buffer insertion and buffer insertion I Interconnect Planning Interconnect Planning I N Physical hierarchy generation Physical hierarchy generation N Floorplan Floorplan/coarse placement with interconnect planning /coarse placement with interconnect planning N Interconnect architecture planning Interconnect architecture planning I Concluding Remarks Concluding Remarks I ASPDAC'01 Tutorial Jason Cong 2

Clock cycles required for traveling 2cm line under BIWS (buffer insertion and wire sizing) 5 4 Estimated by IPEM On NTRS’97 technology clock cycle(s) 3 Driver size: 100x min gate 2 Receiver size: 100x min gate Buffer size: 100x min gate 1 0 5 G Hz 0.25 um 0.18 ym 3 G Hz 0.13 um 0.10 um 0.07 um 1 G Hz ASPDAC'01 Tutorial Jason Cong 3

How Far Can We Go in Each Clock Cycle 7 clock I NTRS’97 0.07um Tech I 5 G Hz across-chip clock 6 clock I 620 mm 2 (24.9mm x 24.9mm) I IPEM BIWS estimations 5 clock N Buffer size: 100x N Driver/receiver size: 100x I From corner to corner: N 7 clock cycles 4 clock 1 clock 2 clock 3 clock 15.04 22.56 24.9 (mm) 0 7.52 ASPDAC'01 Tutorial Jason Cong 4

Two Important Implications I Interconnects determine the system Interconnects determine the system I performance performance Interconnect/communication-centric design methodology I Need multiple clock cycles to cross the global Need multiple clock cycles to cross the global I interconnects in giga interconnects in giga- -hertz designs hertz designs Pipelining/retiming on global interconnects ASPDAC'01 Tutorial Jason Cong 5

Interconnect-Centric Design Methodology I Proposed transition Proposed transition I interconnect device device interconnect device/function centric interconnect/communication centric I Analogy Analogy I Data/Objects Programs Programs Data/Objects ASPDAC'01 Tutorial Jason Cong 6

Interconnect-Centric IC Design Flow Under Development at UCLA Architecture/Conceptual-level Design Design Specification Interconnect Planning Interconnect Performance • Physical Hierarchy Generation Estimation Models (IPEM) HDM • Foorplan/Coarse Placement with Interconnect Planning • OWS, SDWS, BISWS • Interconnect Architecture Planning abstraction Synthesis and Placement under Physical Hierarchy Structure view Functional view Interconnect Optimization Interconnect Synthesis Physical view (TRIO) Performance-driven Global Routing Timing view • Topology Optimization with Buffer Insertion • Wire sizing and spacing Pseudo Pin Assignment under Noise Control • Simultaneous Buffer Insertion and Wire Sizing • Simultaneous Topology Construction with Buffer Insertion and Wire Sizing Interconnect Layout Route Planning Point-to-Point Gridless Routing Final Layout ASPDAC'01 Tutorial Jason Cong 7

Interconnect-Centric IC Design Flow Under Development at UCLA Architecture/Conceptual-level Design Design Specification Interconnect Planning Interconnect Performance Interconnect Planning Estimation Models (IPEM) Interconnect Performance • Physical Hierarchy Generation • Physical Hierarchy Generation Estimation Models (IPEM) • OWS • Foorplan/Coarse Placement with HDM • Foorplan/Coarse Placement with Interconnect Planning • OWS, SDWS, BISWS • SDWS • Interconnect Architecture Planning Interconnect Planning • BISWS • Interconnect Architecture Planning abstraction Synthesis and Placement under Physical Hierarchy Structure view Interconnect Optimization (TRIO) Interconnect Synthesis Functional view Interconnect Optimization Interconnect Synthesis • Topology Optimization with Physical view Performance-driven Global Routing (TRIO) Performance-driven Global Routing Timing view Buffer Insertion • Topology Optimization with Buffer Insertion • Wire sizing and spacing • Wire sizing and spacing Pseudo Pin Assignment under Noise Control Pseudo Pin Assignment under Noise Control • Simultaneous Buffer Insertion and Wire Sizing • Simultaneous Topology Construction • Simultaneous Buffer Insertion with Buffer Insertion and Wire Sizing Interconnect Layout and Wire Sizing Interconnect Layout • Simultaneous Topology Construction Route Planning Route Planning with Buffer Insertion and Wire Sizing Point-to-Point Gridless Routing Point-to-Point Gridless Routing Final Layout ASPDAC'01 Tutorial Jason Cong 8

Interconnect-Centric IC Design Flow Under Development at UCLA Architecture/Conceptual-level Design Design Specification Interconnect Planning Interconnect Performance • Physical Hierarchy Generation Estimation Models (IPEM) HDM • Foorplan/Coarse Placement with Interconnect Planning • OWS, SDWS, BISWS • Interconnect Architecture Planning abstraction Synthesis and Placement under Physical Hierarchy Structure view Functional view Interconnect Optimization Interconnect Synthesis Physical view (TRIO) Performance-driven Global Routing Timing view • Topology Optimization with Buffer Insertion • Wire sizing and spacing Pseudo Pin Assignment under Noise Control • Simultaneous Buffer Insertion and Wire Sizing • Simultaneous Topology Construction with Buffer Insertion and Wire Sizing Interconnect Layout Route Planning Point-to-Point Gridless Routing Final Layout ASPDAC'01 Tutorial Jason Cong 9

Part V Outline I Interconnect Interconnect- -Centric Design Flow Centric Design Flow I I Interconnect Performance Estimation Models Interconnect Performance Estimation Models I N IPEM for optimal IPEM for optimal wiresizing wiresizing N N IPEM for IPEM for wiresizing wiresizing and buffer insertion and buffer insertion N I Interconnect Planning Interconnect Planning I N Physical hierarchy generation Physical hierarchy generation N N Floorplan Floorplan/coarse placement with interconnect /coarse placement with interconnect N planning planning N Interconnect architecture planning Interconnect architecture planning N I Concluding Remarks Concluding Remarks I ASPDAC'01 Tutorial Jason Cong 10

Interconnect Performance Estimation I Introduction & Motivation Introduction & Motivation I I Problem Formulation Problem Formulation I I Interconnect Delay Estimation Models under Various Interconnect Delay Estimation Models under Various I Layout Optimizations Layout Optimizations I Application and Conclusion Application and Conclusion I ASPDAC'01 Tutorial Jason Cong 11

Impact of Interconnect Optimization on Future Technology Generations 5 2cm DS 4.5 4 2cm BIS 3.5 Delay (ns) 2cm BISWS 3 2.5 G DS: Driver Sizing only 2 G BIS: Buffer Insertion 1.5 and Sizing 1 G BISWS: Simultaneous 0.5 Buffer Insertion/Sizing 0 and Wiresizing 0.25 0.18 0.15 0.13 0.1 0.07 Technology ( u m) ASPDAC'01 Tutorial Jason Cong 12

Complexity of Existing Interconnect Opt. Algorithms I 2cm line, W=20, B=10, segment every 500um 2cm line, W=20, B=10, segment every 500um I I Use Use best available best available algorithms: algorithms: I N Local Refinement ( Local Refinement (LR LR) ) N Dynamic Programming ( Dynamic Programming (DP DP) ) N Hybrid of Hybrid of DP+LR DP+LR DP DP+LR LR Algorithm OWS BI+OWS BIWS BISWS Delay (ns) 4.5 1.6 1.02 0.81 CPU (s) 0.06 0.42 4.5 12.4 ( HSPICE needs additional 60 seconds! ) ( HSPICE needs additional 60 seconds! ) ASPDAC'01 Tutorial Jason Cong 13

Needs for Efficient Interconnect Estimation Models I Efficiency Efficiency I I Abstraction Abstraction to hide detailed design information to hide detailed design information I N granularity of wire segmentation granularity of wire segmentation N number of wire widths, buffer sizes, ... number of wire widths, buffer sizes, ... I Explicit relation Explicit relation to enable optimal design decision at to enable optimal design decision at I high levels high levels I Ease of interaction Ease of interaction with logic/high level synthesis tools with logic/high level synthesis tools I ASPDAC'01 Tutorial Jason Cong 14

Interconnect Performance Estimation Modeling [Cong-Pan, ASPDAC’99, TAU’99, DAC’99] I Develop a set of Develop a set of interconnect performance estimation interconnect performance estimation I models ( (IPEM IPEM), under different optimization alternatives: ), under different optimization alternatives: models N Optimal Wire Sizing Optimal Wire Sizing (OWS) (OWS) N Simultaneous Driver and Wire Sizing Simultaneous Driver and Wire Sizing (SDWS) (SDWS) N Simultaneous Buffer Insertion and Wire Sizing Simultaneous Buffer Insertion and Wire Sizing (BIWS) (BIWS) N Simultaneous Buffer Insertion/Sizing and Wire Sizing Simultaneous Buffer Insertion/Sizing and Wire Sizing (BISWS) (BISWS) I IPEM have IPEM have I N closed closed- -form formula or simple characteristic equations form formula or simple characteristic equations N constant running time in practice constant running time in practice N high accuracy (about 90% accuracy on average) high accuracy (about 90% accuracy on average) ASPDAC'01 Tutorial Jason Cong 15