[PPT] - Nanostructures for Tera Tera- -bit Level bit Level Nanostructures PowerPoint Presentation

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N a n

F
r

u m' 9

Nanostructures for Nanostructures for Tera Tera-

bit Level

bit Level Charge Trap Flash Memories Charge Trap Flash Memories

Byung-Gook Park, Il Han Park, Jung-Hoon Lee, Gil Sung Lee, Jang-Gn Yun Inter-University Semiconductor Research Center School of Electrical Eng. and Computer Sci. Seoul National University

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Outline

I. I. Introduction Introduction II. NAND Cell Structure

III. NOR Cell and Array Structure
IV. AND Cell and Array Structure
V. STAR NAND Flash Structure
VI. Conclusions

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Flash Memory and Mobile Equipments

32

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Expedited Growth Theory Expedited Growth Theory -

NAND Flash

NAND Flash

Expedited growth theory of NAND flash memories Year 2011 1Tb capacity with 20nm feature size

2002 2004 2006 2008 2010 2012 2014 2016 2018 10 100

ITRS (2008) Hwang’s law

Year of Development Technology Node (nm)

10 100 1000

Capacity (Giga Bit)

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Hard Disk Drive and Flash Memory Hard Disk Drive and Flash Memory

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Growth of Storage Capacity Growth of Storage Capacity

1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 1k 10k 100k 1M 10M 100M 1G 10G 100G 1T 10T

Capacity (bit) Year

HDD ODD FGF CTF FeRAM MRAM PRAM

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Floating Gate vs. Charge Traps Floating Gate vs. Charge Traps

No floating gate

FG-FG space
FG-active space
Single gate structure

Gate

Floating Gate structure SONOS structure

Gate

P

Si

P

Si

ONO Composite Dielectrics n+ n+ n+ n+

Gate

Floating Gate structure SONOS structure

Gate

P

Si

P

Si

ONO Composite Dielectrics n+ n+ n+ n+

Tunnel Blocking Si SiO2 Si3N4 SiO2 Poly Si

3.1 3.8 8.0 1.05 1.85 3.1 3.8

e e e h h h

Tunnel Blocking Si SiO2 Si3N4 SiO2 Poly Si

3.1 3.8 8.0 1.05 1.85 3.1 3.8

e e e h h h

Defect immunity

Non-conductive trap layer
Discrete trap storage

3D structure compatibility

Insulating storage node
Simple fabrication

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Outline

I. Introduction II. II. NAND Cell Structure NAND Cell Structure

III. NOR Cell and Array Structure
IV. AND Cell and Array Structure
V. STAR NAND Flash Structure
VI. Conclusions

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Arch Structure (1) Arch Structure (1)

Utilization of curved surfaces for field enhancement

fast “program” and “erase”
increased effective area

SiO

2

Si Poly ONO

r

2

r

1

r

2

r

1

2 4 6 8 10 12 14 0.0 2.0M 4.0M 6.0M 8.0M 10.0M 12.0M Bottom Oxide Silicon Nitride

Electric Field (V/cm) Position (nm)

Arch type Planar type Top Oxide

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Arch Structure (2) Arch Structure (2)

Hard mask Si Si SiO

2

Si

Fabrication procedure

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Arch Structure (3) Arch Structure (3)

Utilization of HSQ mask characteristic Planarization by TEOS, HSQ and etch back

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Arch Structure (4) Arch Structure (4)

<Programming characteristics> <Erase characteristics>

10

7 10
6 10
5 10
4 10
3 10
2 10
1 10

0 10 1

0.5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Initial

20V 22V 24V

∆Vth (V)

Time(s) 10

7 10
6 10
5 10
4 10
3 10
2 10
1 10

0 10 1

6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5

0.0 0.5

Initial

18V
20V
22V
24V

∆Vth (V)

Time(s)

Radius of Si channel = 15 nm

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Outline

I. Introduction II. NAND Cell Structure III.

III. NOR Cell and Array Structure

NOR Cell and Array Structure

IV. AND Cell and Array Structure
V. STAR NAND Flash Structure
VI. Conclusions

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Cone Structure (1) Cone Structure (1)

Utilization of field and current concentration

field concentration in the horizontal direction
current concentration in the vertical direction

Drain

r1 r2 Er ER

Source

Cut line

Gate Drain junction ONO layer

flux

Electric field high flux density low flux density Cut line

Gate Drain junction ONO layer

Gate Si O O N

high flux density low flux density

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Cone Structure (2) Cone Structure (2)

Simple array structure

common source architecture
word line connection through small spacing of cones

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Cone Structure (3) Cone Structure (3)

<Plan view> <Cross-sectional view>

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Cone Structure (4) Cone Structure (4)

Electrical characteristics

1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

CHEI Program( VG: 6 V, VD:4 V)

VTH ( V) Time (s)

CHEI Program( VG: 6 V, VD:3 V) FN Erase ( VB : 11 V)

10 10

1

10

2

10

3

10

4

10

5

10

6

10

7

10

8

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

2.160 V Erase state

VTH (V)

Time (s)

Retention Characteristics(150

C)

program state 2.363 V

<Program/erase characteristics> <Retention characteristic>

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Outline

I. Introduction II. NAND Cell and Array Structure

III. NOR Cell and Array Structure

IV.

IV. AND Cell and Array Structure

AND Cell and Array Structure

V. STAR NAND Flash Structure
VI. Conclusions

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

low low high density high high low sensing speed high Low high program efficiency AND NOR NAND

W/L F-Poly LSL LBL Active

Schematic Top View

< NAND > < NOR > < AND >

Conventional Flash Memory Structures Conventional Flash Memory Structures

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Memory cell device with vertical and double gate structures

vertical structure, S/D junctions connected by diffusion layer

High integration density.

double gate structure.

High device performance, high sensing speed.

N N P N N P P N N P N N P N N P P N N P N N P N N P P N N P

Vertical AND Structure (1) Vertical AND Structure (1)

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N N P N N P N P P N P P N N P N N P P N N P N N N N N P P N N P N N P P N N P N N N P P N N P N N P P N N P N N N N P N N P P N N P N N P N P N N P N N P P N N P N N P N P N N P N N P P N N P N N P N P N N N P N N P P N N P N N P N P N

(a) (b) (c) (d) (e) (f) (g) (h)

Vertical AND Structure (2) Vertical AND Structure (2)

Fabrication procedure

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Vertical AND Structure (3) Vertical AND Structure (3)

10

7

10

6

10

5

10

4

10

3

10

2

10

1

2 3 4 5 6 7

Threshold Voltage [V] Programming Time (sec)

VG = 13 V VG = 15 V VG = 17 V

10

5

10

4

10

3

10

2

10

1

10 2 3 4 5 6 7

Threshold Voltage [V] Erasing Time (sec)

VG = 13 V VG = 15 V VG = 17 V

<Program characteristics> <Erase characteristics> Program/erase characteristics

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Outline

I. Introduction II. NAND Cell Structure

III. NOR Cell and Array Structure
IV. AND Cell and Array Structure

V.

V. STAR NAND Flash Structure

STAR NAND Flash Structure

VI. Conclusions

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Stacked bit-lines high density Cylindrical channel and gate-all-around cell structure high performance Single-crystal Si channel high performance, uniformity, reliability

STAR NAND Flash Structure (1)

Si substrate Si

xide

Si

xide

gate cylindrical channel ONO dielectrics gate body WL direction

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Si substrate SiGe Si SiGe Si SiGe nitride Si substrate SiGe Si SiGe Si SiGe nitride Si substrate SiGe Si SiGe Si SiGe nitride mask a > b Si substrate SiGe Si SiGe Si SiGe nitride a > b Si substrate Si Si nitride SiGe Si substrate Si Si nitride SiGe

STAR NAND Flash Structure (2)

Fabrication procedure

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Si substrate nitride Si Si ONO Si substrate Si ONO SiGe Si gate Si Si substrate Si

xide

Si

xide

gate cylindrical channel ONO dielectrics gate body WL direction

STAR NAND Flash Structure (3)

Fabrication procedure (continued)

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STAR NAND Flash Structure (4)

Components of stack and nanowire implementation <Selectively etched SiGe> <Rounded Si nanowire>

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Conclusions (1)

Charge trap flash memory including SONOS structure is a promising candidate for the next generation high density flash memories. For NAND application, arch SONOS flash memory is proposed for field concentration and suppression of back tunneling and is successfully demonstrated. For NOR application, cone SONOS flash memory is proposed for field and current concentration, and the fabricated cell shows superb electrical characterics.

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NanoForum'09 SNU SNU SoEECS SoEECS & ISRC & ISRC

Conclusions (2)

For AND application, vertical AND structure is proposed for drastic reduction of cell size and the feasibility is demonstrated. For further increase of density, STacked ARray (STAR) NAND array is proposed.