Nanometer-Scale III-V CMOS J. A. del Alamo Microsystems Technology - PowerPoint PPT Presentation

Nanometer-Scale III-V CMOS J. A. del Alamo Microsystems Technology Laboratories, MIT Short Course on The Future of Semiconductor Devices and Integrated Circuits 34 th IEEE Compound Semiconductor IC Symposium Oct. 14th, 2012 Acknowledgements: • D. Antoniadis, D.-H. Kim, T.-W. Kim, D. Jin, J. Lin, N. Waldron, L. Xia • Sponsors: Intel, FCRP-MSD • Labs at MIT: MTL, NSL, SEBL 1

Outline 1. The CMOS revolution 2. Materials options for post-Si CMOS 3. What have we learned from III-V HEMTs? 4. III-V CMOS device design and challenges – Critical issue #1: the gate stack – Critical issue #2: the ohmic contacts – Critical issue #3: the p-channel device – Critical issue #4: non-planar MOSFET designs – Critical issue #5: co-integration of nFETs and pFETs 5. Concluding remarks 2

1. The CMOS Revolution: Smaller is Better! Virtuous cycle of scaling  exponential improvements in: – Transistor density (“Moore’s law”) – Performance – Power efficiency Intel microprocessors Intel microprocessors 3

The Si CMOS Revolution: Smaller is Better! Koomey, Ann. Hist. Computing 2011 Year of introduction 4

CMOS scaling in the 21 st century Si CMOS has entered era of “power-constrained scaling”: – Microprocessor power density saturated at ~100 W/cm 2 – Microprocessor clock speed saturated at ~ 4 GHz Intel microprocessors Pop, Nano Res 2010 5

Consequences of Power Constrained Scaling Power = active power + stand-by power 2 N N ↑  V DD ↓ P A ~ f CV DD clock frequency #1 goal! transistor capacitance operating voltage transistor count  Transistor scaling requires reduction in supply voltage 6

CMOS power supply scaling Recently, V DD scaling very … because Si performance weakly… degrades as V DD ↓ 40 nm strained-Si MOSFET (Intel) Dewey, IEDM 2009  Need scaling approach that allows V DD reduction while enhancing performance 7

How to enable further V DD reduction? • Goals of scaling: – reduce transistor footprint – extract maximum I ON for given I OFF 8

How to enable further V DD reduction? • Goals of scaling: – reduce transistor footprint – extract maximum I ON for given I OFF • The path forward: – increasing electron velocity  I ON ↑  V DD ↓ – tighter carrier confinement  S ↓ 9

2. Materials options for post-Si CMOS Ideally want: • High electron and hole velocity Si: v e ~1.5x10 7 cm/s, v h ~1.2x10 7 cm/s • • High sheet-carrier concentration at low voltage Si: ~6x10 12 cm -2 @1 V • • High enough bandgap energy • Si: E g =1.1 eV • High-quality, reliable MOS gate stack Si: D it ~10 11 eV -1 .cm -2 • • Same material for n-channel and p-channel device • Easily integrable on Si substrate • Manufacturable technology (top down, ex-situ dielectrics) 10

Bandgap energy T=300 K 2.8 2.8 2.8 adapted from Bennett adapted from Bennett AlP AlP 2.4 2.4 2.4 AlAs AlAs 2.0 2.0 2.0 GaP GaP Energy Gap (eV) Energy Gap (eV) AlSb AlSb 1.6 1.6 1.6 InP InP ~2x Si GaAs GaAs 1.2 1.2 1.2 Si Si 0.8 0.8 0.8 GaSb GaSb ~2x Si ~0.5x Si Ge Ge 0.4 0.4 0.4 InSb InSb InAs InAs 0 0 0 5.4 5.4 5.4 5.6 5.6 5.6 5.8 5.8 5.8 6.0 6.0 6.0 6.2 6.2 6.2 6.4 6.4 6.4 Lattice Constant (Å) Lattice Constant (Å) InAs, InSb problematic but strong quantum confinement can be used to enhance effective bandgap 11

Use mobility as proxy for velocity 300 K quantum-well or inversion layer mobility at any sheet carrier concentration: ~2x Si GaAs, InP, GaSb: promising ~2x Si for nFET Ge: borderline nFET Ge, GaSb, InSb: borderline pFET GaAs: ruled out for pFET del Alamo, Nature 2011 12

The role of compressive biaxial strain ~2x Si ~2x Si InAs: hurts nFET (need tensile strain) Ge, GaSb, InSb: big pFET improvement (µ>1,000 cm 2 .V.s) 13

What about ternary III-Vs? ~2x Si ~2x Si InGaAs: promising for nFET InGaSb: promising for pFET InGaAs: borderline for pFET 14

D it close to band edges D it (cm 2 /V.s) InGaAs GaSb 10 13 GaSb GaAs GaAs, GaSb: ruled out for nFET GaSb, InGaAs: ruled out for pFET GaAs 10 12 InGaAs Little known about InAs or InSb InP Ge Ge 10 11 E v E c Energy in bandgap Buried-channel structures still possible for narrow-bandgap materials but need to provide appropriate band discontinuity 15

Options for post-Si CMOS InGaAs nFET InP nFET ~2x Si Ge nFET InGaSb pFET Ge pFET ~2x Si Different lattice constants for n-channel and p-channel devices (except for Ge) 16

3. What have we learned from III-V HEMTs? The High Electron Mobility Transistor is now >30 years old! Mimura, JJAPL 1980 17 17 17 17

PHEMT ICs UMTS-LTE PA module Chow, MTT-S 2008 77 GHz transceiver 40 Gb/s modulator driver Tessmann, GaAs IC 1999 Carroll, MTT-S 2002 Bipolar/E-D PHEMT process Henderson, Mantech 2007 PHEMT MMIC market=$1.2B in 2011 Single-chip WLAN MMIC, Morkner, RFIC 2007 18

Near-THz III-V FETs f T in III-V FETs vs time: Current record: f T =688 GHz f max =800 GHz Kim IEDM 2011 (Teledyne/MIT) (and MHEMT) (and MHEMT) Current f max record: f max =1.25 THz Kim IEDM 2010 (Teledyne/MIT) • For >20 years, record f T obtained on InGaAs-channel HEMTs • InGaAs-channel HEMTs offer record of balanced f T and f max 19

III-V HEMTs: excellent model system to explore logic suitability of III-Vs State-of-the-art: InAs HEMTs Gate S D Oxide - QW channel (t ch =10 nm): Cap • InAs core (t InAs = 5 nm) Etch stopper Barrier t ins • InGaAs cladding t ch   n,Hall =13,200 cm 2 /V-sec Channel Buffer - InAlAs barrier (t ins =4 nm) - Ti/Pt/Au Schottky gate - L g =30 nm Kim, EDL 2010 20 20 20 20

L g =30 nm InAs HEMT Kim, EDL 2010 2.0 V GS = 0.8 0.4 V 1.5 0.6 g m [mS/  m] I D [mA/  m] 0.2 V 1.0 0.4 0.5 0.2 0 V V DS = 0.5 V 0.0 0.0 0.0 0.2 0.4 0.6 0.8 -0.6 -0.4 -0.2 0.0 0.2 V DS [V] V GS [V] • Large current drive: I ON >0.5 mA/µm at V DD =0.5 V • High transconductance: g mpk = 1.9 mS/ μ m at V DD =0.5 V • V T = -0.15 V, R S =190 ohm. μ m 21 21 21 21

L g =30 nm InAs HEMT 40 3 Kim, EDL 2010 H 21 30 2 U g Gains [dB] MSG/MAG 20 1 K f T = 644 GHz 10 0 K f max = 681 GHz V DS =0.5 V, V GS =0.2 V 0 -1 9 10 11 12 10 10 10 10 Frequency [Hz] • First transistor of any kind with both f T and f max > 640 GHz • Current record is f T , f max > 688 GHz from Teledyne/MIT collaboration (Kim, IEDM 2011) 22 22 22 22

30 nm InAs HEMT – Logic characteristics -3 10 V DS = 0.5 V -4 10 V DS = 0.05 V I D -5 10 I D , I G [A/  m] -6 10 V DS = 0.5 V -7 10 I G -8 10 V DS = 0.05 V -9 10 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 V GS [V] • S = 74 mV/dec, DIBL = 80 mV/V Kim, EDL 2010 23 23 23 23

30 nm InAs HEMT – Logic characteristics I ON =0.52 mA/ μ m -3 10 V DS = 0.5 V Kim, EDL 2010 -4 10 V DS = 0.05 V I D -5 10 I D , I G [A/  m] -6 10 V DS = 0.5 V I OFF =100 nA/ μ m -7 10 I G -8 10 V DS = 0.05 V -9 10 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 V GS [V] 0.5 V • S = 74 mV/dec, DIBL = 80 mV/V • At I OFF =100 nA/ μ m and V DD =0.5 V, I ON =0.52 mA/ μ m 24 24 24 24

InAs HEMTs: Benchmarking with Si FOM that integrates short-channel effects and transport: I ON @ I OFF =100 nA/µm, V DD =0.5 V Kim EDL 2010 Kim IEDM 2008 InAs HEMTs: higher I ON for same I OFF than Si. Why? 25

Why high I ON ? 1. Very high electron injection velocity at the virtual source v inj E C E V Kim, IEDM 2009 Liu, Springer 2010 Khakifirooz, TED 2008 del Alamo, Nature 2011 • v inj (InGaAs) increases with InAs fraction in channel • v inj (InGaAs) > 2v inj (Si) at less than half V DD • ~100% ballistic transport at L g ~30 nm 26

Why high I ON ? 2. Quantum capacitance less of a bottleneck than previously believed InAs channel: t ch = 10 nm 40 Experiment (C G ) C ins ( t ins = 4 nm) Capacitance [fF/  m 2 ] 30 C Q1 (m ||* = 0.026m e ) 20 C cent1 C G ( 0.07 ) 10 C G ( 0.05 ) C G (m ||* = 0.026m e ) Jin, IEDM 2009 0 -0.4 -0.2 0 0.2 0.4 V G [V] Biaxial strain + non-parabolicity + strong quantization: m || * ↑  C G ↑  n s ↑  I ON ↑ 27

Why high I ON ? 3. Sharp subthreshold swing due to quantum-well channel state-of-the-art Si 90 In 0.7 Ga 0.3 As HEMTs: t ch = 13 nm Subtreshold swing [mV/dec] 80 InAs HEMTs: t ch = 10 nm 70 InAs HEMTs: t ch = 5 nm t ins = 4 nm, L side = 80 nm Kim, IPRM 2010 60 40 80 120 160 200 L g [nm] • Dramatic improvement in short-channel effects with thin channel • Thin channel does not degrade v inj at L g ~40 nm (Kim, IPRM 2011) 28

Limit to III-V HEMT Scaling: Gate Leakage Current -3 InAs HEMT 10 t ins = 10 nm L g = 30 nm t ins = 7 nm -4 10 I D t ins = 4 nm t ch = 10 nm -5 10 t ins =4 nm I D , I G [A/  m] -6 10 I G -7 10 t ins =7 nm -8 10 del Alamo. IPRM 2011 -9 t ins =10 nm 10 V DS = 0.5 V -10 10 -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 V GS [V] t ins ↓  I G ↑  Further scaling requires high-K gate dielectric 29 29

4. III-V CMOS: device design and challenges Modern III-V HEMT vs. modern Si MOSFET: Intel’s 45 nm CMOS III-V HEMT ~1  m • What do we preserve? • What do we change? 30