Nanometer-Scale I nGaAs Field-Effect Transistors for THz and CMOS - - PowerPoint PPT Presentation

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Nanometer-Scale I nGaAs Field-Effect Transistors for THz and CMOS - - PowerPoint PPT Presentation

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Nanometer-Scale I nGaAs Field-Effect Transistors for THz and CMOS Technologies J. A. del Alamo Microsystems Technology Laboratories, MIT ESSDERC-ESSCIRC 2013 Bucharest, Romania, September 16-20, 2013 Acknowledgements: D. Antoniadis, A.

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SLIDE 1

1

Nanometer-Scale I nGaAs Field-Effect Transistors for THz and CMOS Technologies

  • J. A. del Alamo

Microsystems Technology Laboratories, MIT

Acknowledgements:

  • D. Antoniadis, A. Guo, D.-H. Kim, T.-W. Kim, D. Jin, J. Lin, N. Waldron, L. Xia
  • Sponsors: Intel, FCRP-MSD, ARL, SRC
  • Labs at MIT: MTL, NSL, SEBL

ESSDERC-ESSCIRC 2013

Bucharest, Romania, September 16-20, 2013

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SLIDE 2
  • 1. InGaAs HEMT today
  • 2. InGaAs HEMTs towards THz operation
  • 3. InGaAs MOSFETs: towards sub-10 nm

CMOS

2

Outline

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SLIDE 3
  • Invention of AlGaAs/GaAs HEMT: Fujitsu Labs. 1980
  • First InAlAs/InGaAs HEMT on InP: Bell Labs. 1982
  • First AlGaAs/InGaAs Pseudomorphic HEMT: U. Illinois 1985
  • Main attraction of InGaAs: RT μe = 6,000~30,000 cm2/V.s

A bit of perspective…

3

Mimura, JJAPL 1980 Ketterson, EDL 1985 Chen, EDL 1982

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SLIDE 4

4

Bipolar/E-D PHEMT process

Henderson, Mantech 2007 40 Gb/s modulator driver Tessmann, GaAs IC 1999 77 GHz transceiver Carroll, MTT-S 2002 UMTS-LTE PA module Chow, MTT-S 2008 Single-chip WLAN MMIC, Morkner, RFIC 2007

I nGaAs Electronics Today

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SLIDE 5

I nGaAs High Electron Mobility Transistor (HEMT)

5

Modulation doping:  2-Dimensional Electron Gas at InAlAs/InGaAs interface

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SLIDE 6

100 200 300 400 500 600 700 800 1980 1990 2000 2010

fT (GHz) Year

I nGaAs HEMT: high-frequency record vs. time

6

  • Highest fT of any FET on any material system
  • Best balanced fT and fmax of any transistor on any material

Teledyne/MIT: fT=688 GHz, fmax=800 GHz Devices fabricated at MIT

  • n GaAs substrate
  • n InP

substrate fT=710 GHz fmax=478 GHz Chang, APEX 2013 (NCTU)

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SLIDE 7

I nGaAs HEMTs: circuit demonstrations

7

10-stage 670 GHz LNA 80 Gb/s multiplexer IC

Wurfl, GAAS 2004

6-stage 600 GHz LNA

Tessmann, CSICS 2012 Leong, IPRM 2012 Sarkozy, IPRM 2013

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SLIDE 8

I nGaAs HEMTs on I nP used to map infant universe

8

Full-sky map of Cosmic Microwave Background radiation (oldest light in Universe)  age of Universe: 13.73B years (±1%) WMAP=Wilkinson Microwave Anisotropy Probe Launched 2001

0.1 µm InGaAs HEMT LNA Pospieszalski, MTT-S 2000

http://map.gsfc.nasa.gov/

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SLIDE 9

9

A closer look: I nGaAs HEMTs at MI T

9

  • QW channel (tch = 10 nm):
  • InAs core
  • InGaAs cladding

 e = 13,200 cm2/V-sec

  • InAlAs barrier (tins = 4 nm)
  • Lg = 30 nm

Kim, EDL 2010

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SLIDE 10

10

9

10

10

10

11

10

12

10 20 30 40

Frequency [Hz] Gains [dB]

  • 1

1 2 3

K

H21 K MSG/MAG Ug

10 10

Lg= 30 nm I nGaAs HEMT

10

  • High transconductance: gm= 1.9 mS/μm at VDD=0.5 V
  • First transistor of any kind with both fT and fmax > 640 GHz

10

Kim, EDL 2010

  • 0.6
  • 0.4
  • 0.2

0.0 0.2 0.0 0.5 1.0 1.5 2.0

gm [mS/m] VGS [V]

VDS = 0.5 V

0.0 0.2 0.4 0.6 0.8 0.0 0.2 0.4 0.6 0.8

0.2 V 0.4 V 0 V

ID [mA/m] VDS [V]

VGS =

VDS=0.5 V, VGS=0.2 V

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SLIDE 11

11

How to reach fT = 1 THz?

fT = 1 THz feasible by:  scaling to Lg ≈ 25 nm  ~30% R and C parasitic reduction

100 200 400 600 800 1000 1200

VDS = 0.6 V 30% reduction in all the parasitics

Measured fT Modeled fT Model Projection

fT [GHz] Lg [nm] 1 THz

30

Kim, IEDM 2011

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SLIDE 12

Record fT I nGaAs HEMTs: megatrends

12

  • Over time: Lg↓, InxGa1-xAs channel xInAs↑
  • Lg, xInAs saturated  no more progress possible?

x=0.53

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SLIDE 13

Record fT I nGaAs HEMTs: megatrends

13

  • Over time: tch↓, tins↓
  • tch, tins saturated  no more progress possible?
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SLIDE 14

14

Limit to HEMT barrier scaling: gate leakage current

InGaAs HEMTs

At Lg=30-40 nm, modern HEMTs are at the limit of scaling!

Lg=40 nm VDS=0.5 V

Kim, EDL 2013

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SLIDE 15

15

Solution: MOS gate!

Need high-K gate dielectric: HEMT  MOSFET!

InGaAs HEMTs

10-5x!

Lg=40 nm VDS=0.5 V

Kim, EDL 2013 Al2O3 (3 nm)/InP (2 nm)/InGaAs MOSFET

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SLIDE 16

16

I nGaAs MOSFETs with fT= 370 GHz

(Teledyne/ MI T/ I ntelliEpi/ Sematech)

  • Channel: 10 nm In0.7Ga0.3As
  • Barrier: 1 nm InP + 2 nm Al2O3
  • Lg = 60 nm
  • gm = 2 mS/μm
  • RON = 220 Ω.μm

10

9

10

10

10

11

10 20 30 40 50

fmax = 280 GHz MSG Ug Gains [dB] Frequency [Hz] H21 fT = 370 GHz

VDS=0.5 V

H21

Kim, APL 2012

fT=370 GHz

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SLIDE 17

17

Historical evolution: I nGaAs MOSFETs vs. HEMTs

Ren, EDL 1998 Radosavljevic, IEDM 2009 Wieder, EDL 1981 Lin, IEDM 2013

Progress reflects improvements in oxide/III-V interface

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SLIDE 18

18

Huang, APL 2005

ALD eliminates surface oxides that pin Fermi level:

– First observed with Al2O3, then with other high-K dielectrics – First seen in GaAs, then in other III-Vs

Clean, smooth interface without surface oxides

What made the difference? Oxide/ I I I -V interfaces with unpinned Fermi level by ALD

“Self cleaning”

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SLIDE 19

I nterface quality: Al2O3/ I nGaAs vs. Al2O3/ Si

19

Close to Ec, Al2O3/InGaAs comparable Dit to Al2O3/Si interface

Werner, JAP 2011

Al2O3/Si Al2O3/InGaAs

Brammertz, APL 2009

Ec Ev Ev Ec

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SLIDE 20

I nGaAs n-MOSFET: best candidate for post-Si CMOS

Si CMOS scaling seriously stressed  Moore’s law threatened

20

?

Intel microprocessors

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SLIDE 21

21

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SLIDE 22

CMOS scaling in the 21st century

Si CMOS has entered era of “power-constrained scaling”:

 Microprocessor power density saturated at ~100 W/cm2

22

Pop, Nano Res 2010

Future scaling demands VDD↓

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SLIDE 23
  • Transistor is switch:
  • Goals of scaling:

– reduce transistor footprint – reduce VDD – extract maximum ION for given IOFF

  • The path forward:

– increase electron velocity  ION ↑ – tighten electron confinement  S ↓

23

 use InGaAs!

How to enable further VDD reduction?

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SLIDE 24

Measurements of electron injection velocity in HEMTs: EC vinj

  • vinj(InGaAs) increases with InAs fraction in channel
  • vinj(InGaAs) > 2vinj(Si) at less than half VDD
  • ~100% ballistic transport at Lg~30 nm

Electron injection velocity: I nGaAs vs. Si

Kim, IEDM 2009 Liu, Springer 2010 Khakifirooz, TED 2008 del Alamo, Nature 2011

24

EV

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SLIDE 25

Lg= 30 nm I nGaAs HEMT – Subthreshold characteristics

25

  • S = 74 mV/dec
  • Sharp subthreshold behavior due to tight electron

confinement in quantum well

Kim, EDL 2010

  • 1.0
  • 0.8
  • 0.6
  • 0.4
  • 0.2

0.0 0.2 0.4 10

  • 9

10

  • 8

10

  • 7

10

  • 6

10

  • 5

10

  • 4

10

  • 3

VDS = 0.05 V VDS = 0.5 V

IG ID

VDS = 0.5 V

ID, IG [A/m] VGS [V]

VDS = 0.05 V

Lg=30 nm

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SLIDE 26

Lg= 30 nm I nGaAs HEMT – Subthreshold characteristics

26

  • S = 74 mV/dec
  • At IOFF=100 nA/μm and VDD=0.5 V, ION=0.52 mA/μm

Kim, EDL 2010

  • 1.0
  • 0.8
  • 0.6
  • 0.4
  • 0.2

0.0 0.2 0.4 10

  • 9

10

  • 8

10

  • 7

10

  • 6

10

  • 5

10

  • 4

10

  • 3

VDS = 0.05 V VDS = 0.5 V

IG ID

VDS = 0.5 V

ID, IG [A/m] VGS [V]

VDS = 0.05 V

ION=0.52 mA/μm IOFF=100 nA/μm 0.5 V

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SLIDE 27

FOM that integrates short-channel effects and transport: ION @ IOFF=100 nA/µm, VDD=0.5 V InGaAs HEMTs: higher ION for same IOFF than Si

I nGaAs HEMTs: Benchmarking with Si

27 IEDM 2008 Kim EDL 2010 InGaAs HEMT (MIT)

del Alamo, Nature 2011

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SLIDE 28

n+ n+

I nGaAs MOSFET: possible designs

Regrown S/D QW-MOSFET Trigate MOSFET Nanowire MOSFET Recessed S/D QW-MOSFET

28

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SLIDE 29

Self-Aligned I nGaAs QW-MOSFETs (MI T)

  • Scaled barrier (InP: 1 nm + HfO2: 2 nm)
  • 10 nm thick channel with InAs core
  • Tight S/D spacing (Lside~30 nm)
  • Process designed to be compatible with Si fab

Lin, IEDM 2012

29

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SLIDE 30

30

Lg= 30 nm Self-aligned QW-MOSFET

At VDS = 0.5 V:

  • gm = 1.4 mS/µm
  • S = 114 mV/dec
  • RON = 470 m

Lin, IEDM 2012

  • 0.4
  • 0.2

0.0 0.2 10

  • 8

10

  • 7

10

  • 6

10

  • 5

10

  • 4

10

  • 3

S (mV/dec)

50 mV

ID (A/m) VGS (V)

VDS=0.5 V

Lg=30 nm

80 120 160 200 240 280 320

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SLIDE 31

Scaling and benchmarking

  • Superior behavior to any planar III-V MOSFET to date
  • Matches performance of Intel’s InGaAs Trigate MOSFETs

[Radosavljevic, IEDM 2011]

31

Lin, IEDM 2012 40 80 120 160 100 200 300 400 500

III-V FETs

Ion (A/m) Lg (nm)

Ioff=100 nA/m VDD=0.5 V

MIT HEMT Planar Trigate This work

40 80 120 160 60 80 100 120 140 160

III-V FETs

VDS= 0.5 V

MIT HEMT Planar Trigate This work

Smin (mV/dec) Lg (nm)

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SLIDE 32

Sharp Subthreshold Characteristics

32

  • S = 69 mV/dec at VDS = 50 mV
  • Close to lowest S reported in any III-V MOSFET: 66 mV/dec

[Radosavljevic, IEDM 2011]

  • Aggressively scaled barrier
  • High quality interface: gate last process

Lin, IEDM 2012

Barrier: InP (1 nm) + Al2O3 (0.4 nm) + HfO2 (2 nm)

From:

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SLIDE 33

Regrown source/ drain I nGaAs QW-MOSFET on Si (HKUST)

33

  • MOCVD epi growth on Si wafer
  • n+-InGaAs raised source/drain
  • Self-aligned to gate
  • Composite barrier:

InAlAs (10 nm) + Al2O3 (4.6 nm)

Zhou, IEDM 2012

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SLIDE 34

Characteristics of Lg= 30 nm MOSFET

34

At VDS=0.5 V:

  • gm = 1.7 mS/µm
  • S = 186 mV/dec
  • RON = 157 Ω.µm

Zhou, IEDM 2012

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SLIDE 35

Multiple-gate MOSFETs

# gates ↑  improved electrostatics  enhanced scalability

35

FinFET Trigate Nanowire

Chen, ICSICT 2008

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SLIDE 36

I nGaAs Trigate MOSFET (I ntel)

36

Improved S over planar MOSFET on same heterostructure

Radosavljevic, IEDM 2011

HFIN=40 nm

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SLIDE 37

D = 30 nm

I nGaAs Nanowire MOSFETs

37

Gu, IEDM 2012 D = 20 nm Zhao, IEDM 2013 D = 28 nm Persson, DRC 2012

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SLIDE 38

38

Conclusions: exciting future for I nGaAs

  • Most promising material for ultra-high frequency

and ultra-high speed applications

 first THz transistor?

  • Most promising material for n-MOSFET in a post-

Si CMOS logic technology

 first sub-10 nm CMOS logic?

  • InGaAs + Si integration:

 THz + CMOS + optics integrated systems?