I I I -V High-Electron Mobility Transistors on the path to THz - - PowerPoint PPT Presentation

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I I I -V High-Electron Mobility Transistors on the path to THz - - PowerPoint PPT Presentation

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I I I -V High-Electron Mobility Transistors on the path to THz operation J. A. del Alamo 1 and D.-H. Kim 2 1 Microsystems Technology Laboratories, MIT 2 Previously with Teledyne Scientific, now with Global Foundries I nternational Conference on

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SLIDE 1

I I I -V High-Electron Mobility Transistors

  • n the path to THz operation
  • J. A. del Alamo1 and D.-H. Kim2

1Microsystems Technology Laboratories, MIT 2Previously with Teledyne Scientific, now with Global Foundries

I nternational Conference on Solid State Devices and Materials

Kyoto, Sept. 25-27, 2012

Acknowledgements: Jianqiang Lin, Tae-Woo Kim, Niamh Waldron Sponsors: FCRP-MSD, Intel, SRC, ARL Labs at MIT: MTL, SEBL, NSL

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SLIDE 2

2

Outline

  • 1. High-frequency III-V HEMTs: megatrends
  • 2. State-of-the-art InGaAs HEMTs and fT analysis
  • 3. The path to THz operation
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SLIDE 3
  • 1. I I I -V HEMT: record fT vs. time

3

  • For >20 years, record fT obtained on InGaAs-channel HEMTs
  • InGaAs-channel HEMTs offer record balanced fT and fmax

Current record: fT=688 GHz fmax=800 GHz Kim IEDM 2011 (Teledyne/MIT)

(and MHEMT)

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SLIDE 4

Record fT I I I -V HEMTs: megatrends

4

  • Over time: Lg↓, InxGa1-xAs channel xInAs↑
  • Lg, xInAs saturated  no more progress possible?
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SLIDE 5

Record fT I I I -V HEMTs: megatrends

5

  • Over time: tch↓, tins↓
  • tch, tins saturated  no more progress possible?
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SLIDE 6

6

  • 2. State-of-the-art I nGaAs HEMT

6

  • In0.7Ga0.3As QW channel
  • tch = 10 nm
  • n,Hall > 10,000 cm2/V-sec
  • In0.52Al0.48As barrier + In0.7Al0.3As

spacer (Kim, EL 2011)

  • Dual Si -doping (Kim, IEDM 2010)
  • Pt (3 nm)/Ti/Pt/Au Schottky
  • tins=4 nm
  • InP etch stop (tInP=6 nm)
  • Lside=100 nm
  • Gate stem > 250 nm
  • Mo-based S/D with 2 m S-D spacing

Kim, IEDM 2011

Lg=40 nm InGaAs MHEMT

GaAs substrate

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SLIDE 7

7

TEM cross section

GaAs Substrate Graded Buffer HEMT Epi

Buried Pt Ti Pt Au

S G D

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SLIDE 8

8

Output and transfer characteristics

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  • Large current drive: ID>1 mA/µm at VDS=0.8 V
  • High transconductance: gmpk= 2.75 mS/μm at VDS=0.8 V
  • VT ≈ 0 V, RON=280 Ω.μm

8

Kim, IEDM 2011

0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.4 0.8 1.2 0.5 V

ID [mA/m] VDS [V]

VGS = 0.6 V 0.0 0.2 0.4 0.6 1 2 3 0.8 V 0.2 V

gm [mS/m] VGS [V]

VDS = 0.1 V

Lg=40 nm Lg=40 nm

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SLIDE 9

10

9

10

10

10

11

10

12

20 40

Frequency [Hz] Gains [dB]

1 2 3 4 Stability Factor (k)

High-frequency characteristics

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  • Only transistor of any kind with both fT and fmax > 680 GHz
  • Obtained at same bias point, VDS=0.6 V

9

Kim, IEDM 2011

fT = 688 GHz fmax = 800 GHz

VDS=0.6 V, VGS=0.4 V

h21 MSG Ug k

VDS=0.6 V, VGS=0.4 V

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SLIDE 10

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fT vs. fmax

200 400 600 800 1000 500 1000 1500

MIT/TSC HEMT Fujitsu HEMT NGAS HEMT SNU HEMT UCSB HBT UIUC HBT TSC HBT HRL HBT ETH HBT

m ax

f f

fmax [GHz] fT [GHz]

300 600 700 = favg =

TSC/MIT (This work)

  • Record fT FET
  • Best-balanced fT and fmax transistor

Kim, IEDM 2010 (fmax=1.25 GHz) Kim, IEDM 2011

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SLIDE 11

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ft analysis

  • First-order fT expression for HEMT:

11

gmivgs goi RD RS Cgs Cgd

S D G

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SLIDE 12

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Break out extrinsic capacitances

  • Capacitance components:

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S G D

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SLIDE 13

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Delay time analysis

  • Delay time:
  • Components of delay time:

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Intrinsic delay (transit time) Extrinsic delay Parasitic delay

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SLIDE 14

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Delay components of Lg= 40 nm I nGaAs HEMT

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Delay time from fT: ~231 fs

  • Intrinsic delay: ~81 fs
  • Extrinsic delay: ~99 fs
  • Parasitic delay: ~50 fs
  • Unaccounted: ~9 fs

yields <ve>=5x107 cm/s most significant

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SLIDE 15

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Scaling of delay components

15

ext and par do not scale, become dominant for Lg< 50 nm

100 200 200 400 600

VDS = 0.6 V VGS - VT = 0.3V

Delays [fs] Lg [nm] Transit ext par

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SLIDE 16

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Scaling of small-signal components

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100 200 1000 2000

Cgs_ext Cgs, Cgd [fF/mm] Lg [nm]

VDS = 0.6 V VGS - VT = 0.3V

Cgs Cgd Cgd_ext

do not scale do not scale

↑

↓ As Lg↓:

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SLIDE 17
  • Intrinsic delay ↓  Lg ↓
  • Extrinsic delay ↓:

 Cgsext, Cgdext ↓  gate engineering  gmi ↑  harmonious scaling

  • Parasitic delay ↓:

 RS+RD ↓  S/D engineering  goi/gmi ↓  harmonious scaling

17

  • 3. The path to THz operation

17

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SLIDE 18

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How to reach ft = 1 THz?

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fT = 1 THz feasible by:  scaling to Lg ≈ 25 nm  ~30% parasitic reduction

100 200 400 600 800 1000 1200

VDS = 0.6 V 30% reduction in all the parasitics

Measured fT Modeled fT Model Projection

fT [GHz] Lg [nm] 1 THz

30

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SLIDE 19

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 0.2 0.4 0.6 0.8 1.0 0 V 0.1 V 0.2 V 0.3 V 0.4 V

ID [mA/m] VDS [V]

VGS = 0.5 V

Approach to RS+ RD↓: self-aligned process

19

  • Dry-etched Mo contacts: Rc = 7 Ω.μm
  • Lg=50 nm, RON=290 Ω.μm, gmpk=2.2 mS/μm @ VDS=0.5 V

Lside=100 nm

Kim, IEDM 2010 Waldron, TED 2010

Lg=50 nm

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SLIDE 20

1 10 100 1000 20 40

K MAG/MSG Ug Measured data Modeled data

H21, MAG/MSG and Ug [dB] Frequency [GHz]

K VGS = 0.2 V, VDS = 0.6 V H21

1 2 3 4

Lg= 60 nm self-aligned I n0.7Ga0.3As HEMT

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Highest fT and fmax of any FET at Lg  60 nm

Kim, IEDM 2010

Lg=60 nm

fT=595 GHz fmax=680 GHz

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SLIDE 21

Lg= 30 nm self-aligned I nGaAs MOSFET with Lside~ 30 nm

21

gmpk=1.4 mS/μm RON=475 Ω.µm  access region design critical!

Lin, IEDM 2012

0.0 0.1 0.2 0.3 0.4 0.5 200 400 600

Id (A/m) Vds (V)

Vgs = -0.2 to 0.5 V in 0.1 V step Ron=475 m (at Vgs =0.7 V) Lg = 30 nm

Lside~30 nm

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SLIDE 22

Regrown source and drain regions

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Lch=30 nm InGaAs MOSFET: RON=133 Ω.µm

Zhou, EDL 2012

Lch=55 nm InGaAs MOSFET: RON=199 Ω.µm

Egard, IEDM 2011

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SLIDE 23

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Harmonious scaling: aspect ratio of record ft devices

23

Dimensions verified by XTEM

  • Channel AR: 3 ~ 4
  • Insulator AR: 7 ~ 10

Channel Aspect Ratio: Lg/tch Insulator Aspect Ratio: Lg/tins

For Lg=25 nm  tch~ 7 nm, tins~ 3 nm

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SLIDE 24

24

Limit to HEMT barrier scaling: gate leakage current

24

InAlAs/InGaAs HEMTs

At Lg=30 nm, modern HEMTs are at the limit of scaling!

VDS=0.5 V

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SLIDE 25

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Limit to HEMT barrier scaling: gate leakage current

25

Need high-K gate dielectric: HEMT  MOSFET!

InAlAs/InGaAs HEMTs Al2O3 (3 nm)/InP (2 nm)/InGaAs MOSFET

10-5x!

VDS=0.5 V

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SLIDE 26

I I I -V MOSFET: deep scaling possible

  • 0.2

0.0 0.2 0.4 0.6 10

  • 11

10

  • 10

10

  • 9

10

  • 8

10

  • 7

10

  • 6

S=69 mV/dec Vds=0.5 and 0.05 V Lg= 300m

Id (A/m) Vgs (V)

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S=69 mV/dec  Low Dit at MOS interface demonstrated

Lin, IEDM 2012

InP (1 nm) + Al2O3 (0.4 nm) + HfO2 (2 nm)  EOT ~ 0.9 nm [vs. 4 nm InAlAs  EOT = 1.3 nm]  should bring us to Lg=20 nm Long-channel In0.53Ga0.47As MOSFET μe ≈ 2700 cm2/V.s

Equivalent oxide thickness

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SLIDE 27

High-frequency I nGaAs MOSFETs

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ft=245 GHz, RON=323 Ω.µm, gm=1.7 mS/µm, S=105 mV/dec

Kim, VLSI Tech 2012

Lg=100 nm InGaAs MOSFET with Lside~5 nm, EOT=1.9 nm

Lg=100 nm

μe=4600 cm2/V.s

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SLIDE 28

THz MOSFETs: possible designs

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n+ n+

Regrown S/D QW-MOSFET FinFET Gate-all-around nanowire FET Etched S/D QW-MOSFET

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SLIDE 29

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Conclusions

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  • THz III-V FETs just around the corner

 need to reduce parasitics  need to scale harmoniously

  • Exploding interest on III-V CMOS: huge
  • pportunity for THz III-V electronics!

 fast technology progress  new processes and tools  fundamental research on transport, interface, etc.  Si as substrate for THz electronics