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A fA-Range Low-Power Multi-Channel Digital A fA-Range Low-Power - - PowerPoint PPT Presentation

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DCIS 2010 Intro ROIC times Leakage Integ Test Conclusions 1/30 A fA-Range Low-Power Multi-Channel Digital A fA-Range Low-Power Multi-Channel Digital Read-Out Integrated Circuit for Differential Read-Out Integrated Circuit for

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SLIDE 1

DCIS 2010 1/30 Intro ROIC times Leakage Integ Test Conclusions

A fA-Range Low-Power Multi-Channel Digital A fA-Range Low-Power Multi-Channel Digital Read-Out Integrated Circuit for Differential Mobility Analyzers Read-Out Integrated Circuit for Differential Mobility Analyzers

  • A. Jemni, F. Serra-Graells and L. Teres Teres

aymen.jemni@imb-cnm.csic.es y j Integrated Circuits and Systems (ICAS) Instituto de Microelectrónica de Barcelona. IMB-CNM(CSIC) ( )

November 2010

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 2

DCIS 2010 2/30 Intro ROIC times Leakage Integ Test Conclusions

1 Introduction 2 O C Ch l hi 2 ROIC Channel Architecture 3 Reset times 4 Switch Leakage 5 CMOS Integration and Simulation Results 6 T t E i t 6 Test Environment 7 Conclusions

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 3

DCIS 2010 3/30 Intro ROIC times Leakage Integ Test Conclusions

1 Introduction 2

ROIC Channel Architecture

3

Dead times

3

Dead times

4 Switch Leakage 5

CMOS Integration and Simulation Results

6 Test Environment 7

Conclusions

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 4

DCIS 2010 4/30

Introduction

Intro ROIC times Leakage Integ Test Conclusions

Introduction

 Aerosol identification for di i bi l i t medicine, biology, environment monitoring, security…  Differential Mobility Analyzer  Differential Mobility Analyzer (DMA): ion/particle classification according to mass and charge  L i iti ti ( l  Long acquisition time (several seconds)

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 5

DCIS 2010 5/30

Introduction

Intro ROIC times Leakage Integ Test Conclusions

Introduction

 Aerosol identification for di i bi l i t medicine, biology, environment monitoring, security…  Differential Mobility Analyzer  Differential Mobility Analyzer (DMA): ion/particle classification according to mass and charge  L i iti ti ( l  Long acquisition time (several seconds)  Array of independent and  Array of independent and separated microelectrodes  Parallel signal processing  Fast acquisition time (ms) for the same noise bandwidth

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 6

DCIS 2010 6/30 Intro ROIC times Leakage Integ Test Conclusions

1 Introduction 2 ROIC Channel Architecture 3

Dead times

3

Dead times

4 Switch Leakage 5

CMOS Integration and Simulation Results

6 Test Environment 7

Conclusions

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 7

DCIS 2010 7/30

ROIC Channel Architecture

Intro ROIC times Leakage Integ Test Conclusions

ROIC Channel Architecture

 Main specifications of

Param eter Value Units

 Main specifications of the ROIC  Compact channel area

Channel pitch Micro-electrode resistance 50 ≤50 µm Ω

 Short acquisition time  High current sensitivity

Micro-electrode capacitance ≤2 pF Acquisition time I t l ti (@100 ) 1 : 100 ±1 ms fA

 High current sensitivity  Wide dynamic range  L ti

Input resolution (@100ms) Input dynamic range ±1 80 fA dB Supply voltage 3 3 V

 Low-power operation

Supply voltage Power consumption Temperature (@100ms) 3.3 < 0.5

  • 20:0:30

V mW/Ch ºC

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 8

DCIS 2010 8/30

ROIC Channel Architecture

Intro ROIC times Leakage Integ Test Conclusions

ROIC Channel Architecture

 Integrating A/D Conversion  Full-parallel signal processing.  N i t i l  No input signal multiplexing is required.  Narrow noise  Narrow noise bandwidth.  Minimum crosstalk.  Fixed pattern noise compensation.  Low power CMOS and compact circuits required.

  • A. Jemni et al.

IMB-CNM(CSIC)

q

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SLIDE 9

DCIS 2010 9/30 Intro ROIC times Leakage Integ Test Conclusions

1 Introduction 2

ROIC Channel Architecture

3 Reset times 3 Reset times 4 Switch Leakage 5

CMOS Integration and Simulation Results

6 Test Environment 7

Conclusions

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 10

DCIS 2010 10/30

Reset Times

Intro ROIC times Leakage Integ Test Conclusions

Reset Times

 Novel integration scheme for  Novel integration scheme for in-channel ADC conversion.  High linearity.  Correlated Double Sampling (CDS).  Compact CMOS circuits.

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 11

DCIS 2010 11/30

Reset Times

 f

Intro ROIC times Leakage Integ Test Conclusions

Reset Times

 Novel PDM scheme for minimum reset time during integration:  High linearity.  Correlated double li (CDS) sampling (CDS).  Robust.  Compact CMOS circuits.

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 12

DCIS 2010 12/30 Intro ROIC times Leakage Integ Test Conclusions

1 Introduction 2

ROIC Channel Architecture

3

Dead times

3

Dead times

4 Switch Leakage 5

CMOS Integration and Simulation Results

6 Test Environment 7

Conclusions

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 13

DCIS 2010 13/30

Switch Leakage

Intro ROIC times Leakage Integ Test Conclusions

Switch Leakage

 MOSFET switch non-idealities:  Subthreshold conduction  D/S diffusion diodes leakage

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 14

DCIS 2010 14/30

Switch Leakage

Intro ROIC times Leakage Integ Test Conclusions

Switch Leakage

 MOSFET switch non-idealities:  Proper n-well biasing ( V ) biasing ( Vbulk )  Ileak ≤ 0.5 fA

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 15

DCIS 2010 15/30 Intro ROIC times Leakage Integ Test Conclusions

1 Introduction 2

ROIC Channel Architecture

3

Dead times

3

Dead times

4

Switch Leakage

5 CMOS Integration and Simulation Results 6 Test Environment 7

Conclusions

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 16

DCIS 2010 16/30

CMOS Integration and Simulation Results

Intro ROIC times Leakage Integ Test Conclusions

CMOS Integration and Simulation Results

 Full channel layout in 0.35 µm 2P4M CMOS technology:

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 17

DCIS 2010 17/30

CMOS Integration and Simulation Results

Intro ROIC times Leakage Integ Test Conclusions

CMOS Integration and Simulation Results

 CMOS noise dominate  CMOS noise dominate

  • ver electrode noise

 65% thermal and 35% fli k flicker  Adequate LSB for 1 fA resolution

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 18

DCIS 2010 18/30

CMOS Integration and Simulation Results

Intro ROIC times Leakage Integ Test Conclusions

CMOS Integration and Simulation Results

 PDM transfer function  PDM transfer function  Poor linearity at full- scale

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 19

DCIS 2010 19/30

CMOS Integration and Simulation Results

Intro ROIC times Leakage Integ Test Conclusions

CMOS Integration and Simulation Results

 Local bias generator  Local bias generator  Flat temperature sensitivity

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 20

DCIS 2010 20/30 Intro ROIC times Leakage Integ Test Conclusions

CMOS Integration and Simulation Results CMOS Integration and Simulation Results

 Main performance t f th ROIC

Parameter Value Units Channel pitch 50 µm

parameters of the ROIC channel module

Silicon area 0.12 mm2 Acquisition time Equivalent input noise (@100ms) 1 : 100 0.4 ms fArms q p ( ) Instantaneous dynamic range Overall dynamic range Threshold range ( V ) 84 100 ±250 : ±650

rms

dB dB mV Threshold range ( Vth ) Threshold step ( ∆Vth ) ±250 : ±650 ±10 mV mV Supply voltage 3.3 V Current consumption 110 µA

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 21

DCIS 2010 21/30 Intro ROIC times Leakage Integ Test Conclusions

CMOS Integration and Simulation Results

 First test vehicle prototype:

CMOS Integration and Simulation Results

 First test vehicle prototype:  1 pre-amp block  1 PDM bl k  1 PDM block  10 operative channels with external programming external programming  20 full channels with serial interface  035um CMOS 2P 4M technology (AMS-C35)  Bump bonding

2950µm x 2850µm = 8.4mm2

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 22

DCIS 2010 22/30 Intro ROIC times Leakage Integ Test Conclusions

CMOS Integration and Simulation Results

 Second version with enhanced performance and compact layout:

CMOS Integration and Simulation Results

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 23

DCIS 2010 23/30

CMOS Integration and Simulation Results

Intro ROIC times Leakage Integ Test Conclusions

CMOS Integration and Simulation Results

 High Linearity of the PDM  High Linearity of the PDM  High sensitivity (20Hz/fA)

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 24

DCIS 2010 24/30 Intro ROIC times Leakage Integ Test Conclusions

CMOS Integration and Simulation Results CMOS Integration and Simulation Results

 Main performance parameters of the ROIC channel module

Param eter Value Units Ch l h Channel pitch Silicon area 45 0.054 µm mm2 Acquisition time 1 : 100 ms Equivalent input noise (@100ms) Instantaneous dynamic range Overall dynamic range 0.4 120 100 fArms dB dB Threshold range ( Vth ) Threshold step ( ∆Vth ) ±50 : ±650 ±10 mV mV Supply voltage 3.3 V pp y g Current consumption 110 µA

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 25

DCIS 2010 25/30 Intro ROIC times Leakage Integ Test Conclusions

CMOS Integration and Simulation Results

 Second test vehicle prototype:

CMOS Integration and Simulation Results

 Second test vehicle prototype:  1 pre-amp block  1 PDM bl k  1 PDM block  1 operative channel with external programming external programming  2 full channels with serial interface  035um CMOS 2P 4M technology (AMS-C35)  Wire bonding

2000µm x 1300µm = 2.6mm2

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 26

DCIS 2010 26/30 Intro ROIC times Leakage Integ Test Conclusions

CMOS Integration and Simulation Results

 Complete 128-channel ROIC

CMOS Integration and Simulation Results

 Complete 128 channel ROIC  035um CMOS 2P 4M technology (AMS-C35)  B b di  Bump bonding  Size: 5800µm x 1890µm = 10.96mm2

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 27

DCIS 2010 27/30 Intro ROIC times Leakage Integ Test Conclusions

1 Introduction 2 O C Ch l hi 2 ROIC Channel Architecture 3 3 Dead times 4 Switch Leakage 5 CMOS Integration and Simulation Results 6 T t E i t 6 Test Environment 7 Conclusions

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 28

DCIS 2010 28/30

Test Environment

Intro ROIC times Leakage Integ Test Conclusions

Test Environment

 SiO2 wafer substrate for  SiO2 wafer substrate for low leakage  Flip-chip ROIC  Wire-bonded ROIC carrier for multiple sample testing sample testing  SMD bonding by screen printing  500 GΩ glass sealed hermetic resistors for fA stimulus stimulus

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 29

DCIS 2010 29/30 Intro ROIC times Leakage Integ Test Conclusions

1 Introduction 2 O C Ch l hi 2 ROIC Channel Architecture 3 3 Dead times 4 Switch Leakage 5 CMOS Integration and Simulation Results 6 T t E i t 6 Test Environment 7 Conclusions

  • A. Jemni et al.

IMB-CNM(CSIC)

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SLIDE 30

DCIS 2010 30/30

Conclusions

Intro ROIC times Leakage Integ Test Conclusions

Conclusions  Digital multi-channel read-out integrated circuit for differential mobility analyzers  Dedicated PDM ADC with independent gain  ed cated C t depe de t ga programmability and thermal compensation  Low current (110 µA) and compact ( 0 054 mm2 )  Low current (110 µA) and compact ( 0.054 mm ) channel model in 0.35µm 2P4M CMOS technology  Simulation results agrees with the main specifications  Simulation results agrees with the main specifications

  • f the ROIC

 E i t l lt t d i h t  Experimental results are expected in short …thanks for your attention!

  • A. Jemni et al.

IMB-CNM(CSIC)