[PPT] - I nGaAs Nanoelectronics: from THz to CMOS J. A. del Alamo PowerPoint Presentation

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I nGaAs Nanoelectronics: from THz to CMOS

J. A. del Alamo

Microsystems Technology Laboratories, MIT

Acknowledgements:

D. Antoniadis, A. Guo, D.-H. Kim, T.-W. Kim, D. Jin, J. Lin, N. Waldron, L. Xia
Sponsors: Intel, FCRP-MSD
Labs at MIT: MTL, NSL, SEBL

IEEE International Conference on Electron Devices and Solid-State Circuits

Hong Kong, June 3, 2013

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1. InGaAs HEMT today
2. InGaAs HEMTs towards THz operation
3. InGaAs MOSFETs: towards sub-10 nm

CMOS

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Outline

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Invention of AlGaAs/GaAs HEMT: Fujitsu Labs. 1980
First InAlAs/InGaAs HEMT on InP: Bell Labs. 1982
First AlGaAs/InGaAs Pseudomorphic HEMT: U. Illinois

1985

Main attraction of InGaAs: RT μe = 6,000~30,000 cm2/V.s

A bit of perspective…

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Mimura JJAPL 1980 Ketterson EDL 1985 Chen EDL 1982

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Bipolar/E-D PHEMT process

Henderson, Mantech 2007 40 Gb/s modulator driver Tessmann, GaAs IC 1999 77 GHz transceiver Carroll, MTT-S 2002 UMTS-LTE PA module Chow, MTT-S 2008 Single-chip WLAN MMIC, Morkner, RFIC 2007

I nGaAs Electronics Today

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I nGaAs High Electron Mobility Transistor (HEMT)

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Modulation doping:  2-Dimensional Electron Gas at InAlAs/InGaAs interface

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100 200 300 400 500 600 700 800 1980 1990 2000 2010

fT (GHz) Year

I nGaAs HEMT: high-frequency record vs. time

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Highest fT of any FET on any material system
Best balanced fT and fmax of any transistor on any material

Teledyne/MIT: fT=688 GHz, fmax=800 GHz Devices fabricated at MIT

n GaAs substrate
n InP

substrate fT=710 GHz fmax=478 GHz Chang APEX 2013 (NCTU)

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I nGaAs HEMTs: circuit demonstrations

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10-stage 670 GHz LNA 80 Gb/s multiplexer IC

Wurfl, GAAS 2004

Single-stage 500 GHz LNA

Tessmann, CSIC 2010 Leong, IPRM 2012 Sarkozy, IPRM 2013

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I nGaAs HEMTs on I nP used to map infant universe

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Full-sky map of Cosmic Microwave Background radiation (oldest light in Universe)  age of Universe: 13.73B years (±1%) WMAP=Wilkinson Microwave Anisotropy Probe Launched 2001

0.1 µm InGaAs HEMT LNA Pospieszalski MTT-S 2000

http://map.gsfc.nasa.gov/

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A closer look: I nGaAs HEMTs at MI T

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QW channel (tch = 10 nm):
InAs core
InGaAs cladding

 e = 13,200 cm2/V-sec

InAlAs barrier (tins = 4 nm)
Lg = 30 nm

Kim, EDL 2010

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Frequency [Hz] Gains [dB]

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K

H21 K MSG/MAG Ug

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Lg= 30 nm I nGaAs HEMT

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High transconductance: gm= 1.9 mS/μm at VDD=0.5 V
First transistor of any kind with both fT and fmax > 640 GHz

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Kim, EDL 2010

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0.0 0.2 0.0 0.5 1.0 1.5 2.0

gm [mS/m] VGS [V]

VDS = 0.5 V

0.0 0.2 0.4 0.6 0.8 0.0 0.2 0.4 0.6 0.8

0.2 V 0.4 V 0 V

ID [mA/m] VDS [V]

VGS =

VDS=0.5 V, VGS=0.2 V

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How to reach ft = 1 THz?

fT = 1 THz feasible by:  scaling to Lg ≈ 25 nm  ~30% parasitic reduction

100 200 400 600 800 1000 1200

VDS = 0.6 V 30% reduction in all the parasitics

Measured fT Modeled fT Model Projection

fT [GHz] Lg [nm] 1 THz

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Kim, IEDM 2011

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Record fT I nGaAs HEMTs: megatrends

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Over time: Lg↓, InxGa1-xAs channel xInAs↑
Lg, xInAs saturated  no more progress possible?

x=0.53

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Record fT I nGaAs HEMTs: megatrends

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Over time: tch↓, tins↓
tch, tins saturated  no more progress possible?

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Limit to HEMT barrier scaling: gate leakage current

InGaAs HEMTs

At Lg=30-40 nm, modern HEMTs are at the limit of scaling!

Lg=40 nm VDS=0.5 V

Kim, EDL 2013

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Solution: MOS gate!

Need high-K gate dielectric: HEMT  MOSFET!

InGaAs HEMTs

10-5x!

Lg=40 nm VDS=0.5 V

Kim, EDL 2013 Al2O3 (3 nm)/InP (2 nm)/InGaAs MOSFET

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I nGaAs MOSFETs with fT= 370 GHz

(Teledyne/ MI T/ I ntelliEpi/ Sematech)

Channel: 10 nm In0.7Ga0.3As
Barrier: 1 nm InP + 2 nm Al2O3
Lg = 60 nm
gm = 2 mS/μm
RON = 220 Ω.μm

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10 20 30 40 50

fmax = 280 GHz MSG Ug Gains [dB] Frequency [Hz] H21 fT = 370 GHz

Kim, APL 2012

VDS=0.5 V

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I I I -V MOSFET: a > 30 year pursuit!

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Kohn, EL 1977 Mimura, EL 1978 GaAs GaAs

Poor electrical characteristics due to oxide/semiconductor interface defects  Fermi level pinning

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Recent breakthrough: oxide/ I I I -V interfaces with unpinned Fermi level

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In-situ UHV Ga2O3-Gd2O3 on GaAs Ex-situ ALD Al2O3 on GaAs

Ren, SSE 1997 Ye, EDL 2003

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“Self-cleaning” during ALD

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Huang, APL 2005

ALD eliminates surface oxides that pin Fermi level:

– First observed with Al2O3, then with other high-K dielectrics – First seen in GaAs, then in other III-Vs

Clean, smooth interface without surface

xides

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I nterface quality: Al2O3/ I nGaAs vs. Al2O3/ Si

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Close to conduction band edge, Al2O3/InGaAs shows comparable interface state density to Al2O3/Si interface

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Werner, JAP 2011

Al2O3/Si Al2O3/InGaAs

Brammertz, APL 2009

Ec Ev Ev Ec

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Measurements of electron injection velocity in HEMTs: EC vinj

vinj(InGaAs) increases with InAs fraction in channel
vinj(InGaAs) > 2vinj(Si) at less than half VDD
~100% ballistic transport at Lg~30 nm

Electron injection velocity: I nGaAs vs. Si

Kim, IEDM 2009 Liu, Springer 2010 Khakifirooz, TED 2008 del Alamo, Nature 2011

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EV

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I nGaAs n-MOSFET: best candidate for post-Si CMOS

Si CMOS scaling seriously stressed  Moore’s law threatened

Intel microprocessors

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?

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The III-V view

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The III-V view The Si view

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CMOS scaling in the 21st century

Si CMOS has entered era of “power-constrained scaling”:

 Microprocessor power density saturated at ~100 W/cm2

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Pop, Nano Res 2010

Future scaling demands VDD↓

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Transistor is switch:
Goals of scaling:

– reduce transistor footprint – reduce VDD – extract maximum ION for given IOFF

The path forward:

– increase electron velocity  ION ↑ – tighten electron confinement  S ↓

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 use InGaAs!

How to enable further VDD reduction?

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Lg= 30 nm I nGaAs HEMT – Subthreshold characteristics

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S = 74 mV/dec
Sharp subthreshold behavior due to tight electron

confinement in quantum well

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Kim, EDL 2010

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VDS = 0.05 V VDS = 0.5 V

IG ID

VDS = 0.5 V

ID, IG [A/m] VGS [V]

VDS = 0.05 V

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Lg= 30 nm I nGaAs HEMT – Subthreshold characteristics

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S = 74 mV/dec
At IOFF=100 nA/μm and VDD=0.5 V, ION=0.52 mA/μm

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Kim, EDL 2010

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VDS = 0.05 V VDS = 0.5 V

IG ID

VDS = 0.5 V

ID, IG [A/m] VGS [V]

VDS = 0.05 V

ION=0.52 mA/μm IOFF=100 nA/μm 0.5 V

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FOM that integrates short-channel effects and transport: ION @ IOFF=100 nA/µm, VDD=0.5 V InGaAs HEMTs: higher ION for same IOFF than Si

I nGaAs HEMTs: Benchmarking with Si

29 IEDM 2008 Kim EDL 2010 InGaAs HEMT (MIT)

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I I I -V MOSFET: possible designs

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n+ n+

Regrown S/D QW-MOSFET Trigate MOSFET Nanowire MOSFET Recessed S/D QW-MOSFET

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Self-Aligned I nGaAs QW-MOSFETs (MI T)

Scaled barrier (InP: 1 nm + HfO2: 2 nm)
10 nm thick channel with InAs core
Tight S/D spacing (Lside~30 nm)
Process designed to be compatible with Si fab

Lin, IEDM 2012

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Lside

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Lg= 30 nm Self-aligned QW-MOSFET

At VDS = 0.5 V:

gm = 1.4 mS/µm
S = 114 mV/dec
RON = 470 m

Lin, IEDM 2012

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S (mV/dec)

50 mV

ID (A/m) VGS (V)

VDS=0.5 V

Lg=30 nm

80 120 160 200 240 280 320

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Scaling and benchmarking

Superior behavior to any planar III-V MOSFET to date
Matches performance of Intel’s InGaAs Trigate MOSFETs

[Radosavljevic, IEDM 2011]

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Lin, IEDM 2012 40 80 120 160 100 200 300 400 500

III-V FETs

Ion (A/m) Lg (nm)

Ioff=100 nA/m VDD=0.5 V

MIT HEMT Planar Trigate This work

40 80 120 160 60 80 100 120 140 160

III-V FETs

VDS= 0.5 V

MIT HEMT Planar Trigate This work

Smin (mV/dec) Lg (nm)

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Long-channel I nGaAs MOSFET

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S = 69 mV/dec at VDS = 50 mV
Close to lowest S reported in any III-V MOSFET: 66 mV/dec

[Radosavljevic, IEDM 2011]

Barrier: InP (1 nm) + Al2O3 (0.4 nm) + HfO2 (2 nm)

Lin, IEDM 2012

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Regrown source/ drain I nGaAs QW-MOSFET on Si (HKUST)

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MOCVD epi growth on Si wafer
n+-InGaAs raised source/drain
Self-aligned to gate
Composite barrier:

InAlAs (10 nm) + Al2O3 (4.6 nm)

Zhou, IEDM 2012

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Characteristics of Lg= 30 nm MOSFET

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At VDS=0.5 V:

gm = 1.7 mS/µm
S = 186 mV/dec
RON = 157 Ω.µm

Zhou, IEDM 2012

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Multiple-gate MOSFETs

# gates ↑  improved electrostatics  enhanced scalability

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FinFET Trigate Nanowire

Chen, ICSICT 2008

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I nGaAs Trigate MOSFET (I ntel)

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Improved subthreshold swing as fin is made thinner

Radosavljevic, IEDM 2011

HFIN=40 nm

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I nGaAs Nanowire MOSFET (Purdue)

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Gu, IEDM 2011 Gu, APL 2011 Gu, EDL 2012

Ion = 720 μA/μm (86 μA/wire)
gm = 0.51 mS/μm (61 μS/wire)
S = 150 mV/dec

30x30 nm fin Lch= 50 nm Barrier: 10 nm Al2O3 # wires = 4

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Conclusions: exciting future for I nGaAs

Most promising material for ultra-high frequency

and ultra-high speed applications

 first THz transistor?

Most promising material for n-MOSFET in a post-

Si CMOS logic technology

 first sub-10 nm CMOS logic?

InGaAs + Si integration: