LH LHC-AT ATLAS TG TGC - - PowerPoint PPT Presentation

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LH LHC-AT ATLAS TG TGC - - PowerPoint PPT Presentation

Dec 07, 2023 189 likes •391 views

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SLIDE 1

LH LHC-AT ATLAS TG TGC

  • !,#

!,#, !,# ,

!,#, !,#, ! ,

#,$, #,$, #,$, #,$, #,$, ATLAS !, Open − It#, KEK$ 74

  • 17aK209-11
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SLIDE 2

LHC LHC-AT ATLAS

Large Hadron Collider (LHC) CERN 40 MHz LHC-ATLAS(2026)

  • ! = 14 TeV
  • L = 5 - 7.5 10)* cm-.s-0
  • ””

2019/3/1774 2/11

  • 40 MHz

LHC LHC

  • 100 kHz

1 MHz

  • 2.5 μs

10 μs

TGC

1 MHz 10 kHz

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SLIDE 3

TGC32

  • 1. ASD
  • 2. PS

45 ns 64 ns 1.8 m 12.5 m

  • (18 Gb/s)

3.

  • 2019/3/1774

3/11

  • TGC

ASD PS

  • ATLAS

PS

  • 1. 1 ns
  • 2. LHC

PS

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SLIDE 4
  • 1. Patch-Panel (PP) ASIC
  • 2. DACADC
  • 3. FPGAKintex-7 XC7K325T-2FFG900C
  • 4.

PS

  • 1. PP ASIC

2. 2.1. 2.2. FPGASingle-Event Upset (SEU)

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LH LHC-AT ATLASPS PS

LHC-ATLAS PS

  • 20173 20pA12-9

20183 23aK205-1

ADC DAC PP ASIC

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SLIDE 5

PP ASIC ASIC Phase Locked Loop (PLL) 1 ns ()

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PP PP ASIC IC

2019/3/1774

48

  • PLL

Phase detector

up down

Charge pump

  • 20 MHz
  • PLL

2018

PP ASIC

  • 32
  • 32
  • ASIC
  • 40 MHz

filter

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SLIDE 6

19PP ASIC 48 1 ns 20181225000 2019337 2019

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PP PP ASIC IC

2019/3/1774

  • 0 ℃

20 ℃ 40 ℃ 60 ℃ 80 ℃

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SLIDE 7

AT ATLAS

7/11 2019/3/17l74z

GvaTK!b#$ 61F-A61- (0E nSoMP0E sxp )0E 51, GaT7.5 × 10+, cm#/s#$8itgV 9.8 × 10/ cm#/s#$ 5C7A57 e60,yI2D)40 10#$ s#$U

PS

slide-8
SLIDE 8

60TID

8/11

TI TID

PP ASIC, DAC, ADC, 0.45-8.2 Gy/min0.91 Gy/min

  • DAC

ADC 60

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SLIDE 9

TPS6050

  • 9/11

TI TID

2019/3/1774

  • PP ASIC

>20000 Gy 27 Gy 5 DAC DAC7678 180 Gy 180 Gy 5 ADC ADS7953 246 Gy 180 Gy 5

  • TPS7A85

379 Gy 180 Gy 9

  • TPS6050

80 Gy 180 Gy 1 : TPS6050

  • TPS7A85: Low Drop Out

TPS6050: DC/DC

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SLIDE 10

ATLAS 20189 14pS13-4 12.6 !b#$16SEU SEU

  • M. J. Wirthlin et al. 2014 JINST 9 C01025

1 SEM controllerSEU

10/11 2019/3/1774

SE SEU

PS FPGA SEM Controller

  • FPGA

11VME

  • &

ATLAS

  • SEU

)

  • 1

Integrated luminosity (fb

2 4 6 8 10 12

SEU count

5 10 15 20 ATLAS Work in Progress

= 13 TeV s Phase II Upgrade Study, XC7K325T-2FFG900C Big Wheel, R ~ 13 m

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SLIDE 11

LHC-ATLASTGC

  • PS
  • 1 nsPatch-Panel ASIC

1920181225000

  • 4TID

: 180 Gy, ASIC: 27 Gy

  • ATLASSEM controllerPS

12.6 !b#$16SEU

  • PS

2019/3/1774 11/11

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SLIDE 12

2019/3/1774

Ba Backup

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SLIDE 13
  • Since the number of current PP ASICs is insufficient to cover all the new PS

boards, new PP ASICs have to be produced.

  • The basic specification of the PP ASIC is the same as the one for the

current PP ASIC.

  • Preliminary Design Review was completed on 6th March 2018.
  • 20 prototype PP ASICs have been delivered in Oct 2018.

Ø Process: Silterra Malaysia 180 nm CMOS (Rohm 350 nm CMOS for the current chips) Ø Supply: 1.8 V and 3.3 V (3.3 V only for the current chips) Ø Number of channels per chip: 32 Ø LVDS receivers and 1.8 V CMOS transmitters Ø Variable delay with sub-nanosecond step size

  • Stabilisation using PLL circuits
  • Dynamic range : ~50 ns

(30 ns for the (current chips) Ø Bunch crossing identification with 40 MHz clock Ø Test pulse generator for ASD boards Ø Control with SPI (JTAG for the current chips) Ø Voting logic to mitigate the effect of SEU

Ne New PP AS ASIC IC over erview

12/11 2019/3/1774

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SLIDE 14

Su Summary y of PP PP ASI SIC C prototyp ype sp specification

Design process Silterra 0.18 μs CMOS 6M1P Supply voltage 3.3 V (LVDS Rx, test-pulse generator driver) 1.8 V (PLL, delay line, CMOS input and output) Voltage tolerance: ± 10 % # of channels Group A (16 ch), Group B (16 ch) Timing control resolution < 1 ns Timing control range > 40 ns Timing jitter ~40 ps (LVDS Rx), ~40 ps (variable delay) Temperature range 0 - 80 ℃ Power consumption ~20 mW (previous design: 130 mW)

All requirements are satisfied.

13/11 2019/3/1774

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SLIDE 15

Mass product ction of PP ASIC

The modifications are very simple and already completed.

Before modification After modification

  • Change the gate length of transistor in the decay units for reducing the decay

time for an improved margin.

  • Prototype v.0 has a wrong edge setup of SPI MISO signal. Although it is fine for

use if the device controlling the PP ASIC uses the corresponding edge, as done for prototype v.0 measurement, we modified the circuit for next version.

14/11 2019/3/1774

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SLIDE 16

PS board r > 8 m PS board ASD board

AT ATLAS(T (TID) D)

15/11 2019/3/1774

  • P. R. Sala and S. Vanini, FLUGG: FLUKA + Geant4 Geometry for Simulation in HEP

TID TID ASIC = 1.5(sim)1.5(low dose rate)2(lot) COTs = 1.5(sim)5(low dose rate)4(lot)

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SLIDE 17

SEU 7.5 10#$ cm'(s'* 100 6.910'*+ ⁄ cm( bit

  • M. J. Wirthlin et al. 2014 JINST 9 C01025

PS SEU10'$ ⁄ TGC10'* ⁄ (1500) Soft Error Mitigation (SEM) Controller SEM controller

≦100 ms SEUFPGASEU TGCefficiency10'$

16/11

PS

SE SEU

2019/3/1774

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SLIDE 18
  • 1or2

→SEM Controller

  • 2

→Sector LogicSPI

  • mask
  • 17/11

LH LHC-AT ATLASSE SEM Con

  • ntrol
  • ller

PS FPGA SEM Controller

  • FPGA
  • SPI
  • Mask
  • PS
  • Service Patch Panel

FPGA

  • 2019/3/1774
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SLIDE 19

18/11

LH LHC-AT ATLASSE SEM Con

  • ntrol
  • ller
  • 1or2

→SEM Controller

  • 2

→Sector LogicSPI

  • mask
  • PS

FPGA SEM Controller

  • FPGA
  • Service Patch Panel

SPI

  • FPGA
  • Mask
  • PS
  • Mask

2019/3/1774