L2: FPGA HARDWARE 18-545: ADVANCED DIGITAL DESIGN PROJECT FALL 2016 - - PowerPoint PPT Presentation
L2: FPGA HARDWARE 18-545: ADVANCED DIGITAL DESIGN PROJECT FALL 2016 BRANDON LUCIA Admin stuff Project Proposals happen on Monday Be prepared to give an in-class presentation Lab 1 is due Wednesday, Sept. 14th Reading Assignment #1 due today
18-545: ADVANCED DIGITAL DESIGN PROJECT FALL 2016 BRANDON LUCIA
18-545: FALL 2016
Project Proposals happen on Monday Be prepared to give an in-class presentation Lab 1 is due Wednesday, Sept. 14th Reading Assignment #1 due today Submit a PDF/text file, don't fill in the web form Team assignments are done
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18-545: FALL 2016
Status reports due today No word docs, please! Be specific about what happened/is going to happen Talk about what YOU did/will do, not just what your group did Grades on the way, as general feedback
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18-545: FALL 2016
Overview Why use FPGAs? FPGA Internals
7 Caveat: I will use Xilinx specific terminology since that’s the FPGA company you will be using. Beware that other companies use different terms
Field Programmable Gate Array Array of generic logic gates Gates where logic function can be programmed Programmable interconnection between gates Fielded systems can be programmed i.e. post-fabrication
18-545: FALL 2016
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18-545: FALL 2016
Virtex-5 Development System Xilinx XC5VLX110T FPGA 17280 slices of CLB goodness 256MB DDR2 (SODIMM) DVI Video port VGA port is for input 10/100/1000 Ethernet port Audio Codec (AC97) USB2 port 16x2 LCD, RS-232 Compact Flash card slot Expansion connectors
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18-545: FALL 2016
Overview Why use FPGAs? FPGA Internals
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System designers have a Goldilocks problem Off-the-shelf parts are not efficient enough Custom ASICs cost too much Need a “just right” solution
Difficult to design Large and complex Issues in advanced processes Interconnect delay Device leakage Power density constraints Expensive to design / fabricate Mask set costs Non-recurring engineering costs
Need a high-volume, high-profit market to justify costs!
An efficiency gap exists between ASICs and CPUs
0.01 0.1 1 10 100 1000 10000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Energy Efficiency (MOPS/mW) Area Efficiency (MOPS/mm2)
Microprocessors ASICs DSPs
FPGAs: High package costs ($300+), low NRE costs ASICs: Low package costs (pennies), high NRE costs ($600K+)
Development Cost + Device Cost
impacts total volumes shipped
market windows
Total Units
Additional ASIC costs:
Decreasing FPGA unit cost pushing crossover point to the right ASIC Trend FPGA Trend
(Courtesy Xilinx, Inc.)
FPGA solution has a lower total cost ASIC solution has a lower total cost
18-545: FALL 2016
FPGA Advantages
Higher performance than CPU solution Lower power than CPU solution (usually) Low NRE costs Off-the-shelf part designed by FPGA vendor You are sharing NRE costs with all other customers Fast design time Low time-to-market Fast re-design / re-fabrication time Easy to correct an error, to add functionality, in response to spec change Can even change product after deployment
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18-545: FALL 2016
High per-part costs Good for low to middle volume applications High volume applications should consider ASICs Perhaps use FPGA for prototyping Lower performance than ASIC Higher power than ASIC More specialized design skills than programming a CPU
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Rapid Prototyping Emulation of ASIC design Design exploration Shipping product Networking Military Microsoft Bing Datacenters Reconfigurable Computing Research! (http://parallel.princeton.edu/openpiton/)
18-545: FALL 2016
Overview Why use FPGAs? FPGA Internals
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3 Basic components Configurable Logic Blocks General purpose interconnect I/O Blocks Advanced components Hard macros CPUs Block RAM Multipliers Specialized components DSP blocks
CLB (64 TOTAL) I/O BLOCK (64 TOTAL) GENERAL PURPOSE INTERCONNECT IOBS HAVE DIRECT ACCESS TO ADJACENT CLBS SWITCH MATRIX
(COURTESY XILINX, INC.)
ZOOMED IN VIEW OF THE CLB MATRIX OF THE FPGA SPECIFIC INGRESS AND EGRESS CONNECTION OPTIONS (BLACK DOTS) ARE AVAILABLE EVEN MORE ZOOMED IN VIEW
(COURTESY XILINX, INC.)
EACH MATRIX HAS 5 CONNECTIONS PER SIDE
(COURTESY XILINX, INC.)
ONLY CERTAIN CONNECTION PATTERNS ARE POSSIBLE
(COURTESY XILINX, INC.)
EACH MATRIX HAS 5 CONNECTIONS PER SIDE
18-545: FALL 2016
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Spartan-2 and more recent have different length connections between switch matrices Local roads, limited access roads, interstate highways Routes across entire chip don’t burn lots of short connections
CLBs get more and more stuff crammed in them over time XC3K family had LUT (5 variable input, 2 FF values, 2 outputs), 2 FFs, clock enable, FF reset (direct / global) and 9 muxes ~51 bits of configuration SRAM per CLB
(COURTESY XILINX, INC.)
18-545: FALL 2016
A direct implementation of a truth table, using memory LUT inputs are memory address values LUT outputs are the memory data value
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A B C D F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A B C D F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Can view LUT as 16:1 mux Inputs are mux select Config sets mux data inputs Logically same as 16x1 memory Can compact logic if you can route inputs to mux data inputs
Shift register (16 regs) Small memory (16 bits) “Distributed RAM”
18-545: FALL 2016
Spartan-2 has 2 LUTs (4 input each) feeding a 3rd LUT, 2 FFs (with Preset/Reset, Enable, posedge or negedge clocks) and 16 muxes 12 inputs (plus clock), 4 outputs
(COURTESY XILINX, INC.)
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CLBs are composed of 4 slices Organized as 2 pairs, one of which is optimized for memory access Each slice has 2 FFs and 2 LUTs
(COURTESY XILINX, INC.)
◆Low voltage versions ◆Faster clock rates ◆Different packaging options
(Courtesy Xilinx, Inc.)
FIFO memory chips
◆16 port ATM switch, designed on a single board ◆Design is limited by I/O to memory chips--bring them on-chip
FPGAs (XC3Ks)
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◆Global clock buffering, distribution ◆Digital Clock Manager (DCM): eliminate skew, phase shifts,
multiply or divide clock
◆Block RAM ◆Distributed RAM (repurposed LUTs)
◆SelectIO supports 18 standards (single, differential, various
voltage levels, ....)
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Block RAMs Multipliers CPUs DSPs
HDL IP Blocks
Use LUTs as memories Low density Poor performance
Large-ish dedicated memory blocks Xilinx BRAMs = 18Kb Some configurability Dual-port Data width / depth FIFO, CAM, etc.
18-545: FALL 2016
A lot more details on the embedded CPU
3.ibm.com/chips/techlib/techlib.nsf/productfamilies/CoreConnect_ Bus_Architecture
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Lots of configuration bits LUTs, routing, I/O configuration Xilinx XC2VP30 has >11Mb Configuration storage technologies Volatile SRAM cells Non-volatile FLASH, EEPROM Anti-fuse
Actel anti-fuse WL bit bit_b 6T SRAM cell
18-545: FALL 2016
How to load (scan) configuration bits (bitstream) Connect all configuration registers into single long shift register Serially clock in configuration bits Most designs use standard scan interface (JTAG) developed for test Bitstream source Non-volatile memory On-board FLASH, EEPROM, serial memory External media (CF card) Attached workstation Can encrypt bitstream to conceal configuration 49
18-545: FALL 2016
SRAM-based FPGAs Xilinx Altera Atmel Lattice Semiconductor Flash & antifuse FPGAs Actel Corp. Quick Logic Corp. Lattice Semiconductor Xilinx (system-in-a-package solution)
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