Introduction to Transistor Amplifiers: Concept & Biasing - - PowerPoint PPT Presentation

Introduction to Transistor Amplifiers: Concept & Biasing

Lecture notes: Sec. 5 Sedra & Smith (6th Ed): Sec. 5.4-5.4.6 & 6.3-6.4 Sedra & Smith (5th Ed): Sec. 4.4-4.4.6 & 5.3-5.4

• F. Najmabadi, ECE65, Winter 2012

• A voltage amplifier requires

vo/vi = const. (2 examples are shown below)

• vo/vi can be negative (minus sign

represents a 180o phase shift)

Foundation of Transistor Amplifiers (1)

• MOS transfer function is NOT

linear

• In saturation, however, transfer

function looks linear (but shifted)

• F. Najmabadi, ECE65, Winter 2012

Foundation of Transistor Amplifiers (2)

• F. Najmabadi, ECE65, Winter 2012
• Let us consider the response if NMOS remain in saturation at all times:
• vGS should be a combination of a constant value (VGS) and a signal (vgs).

gs GS GS

v V v + =

The response to a combination of vGS = VGS + vgs can be found from the transfer function

• F. Najmabadi, ECE65, Winter 2012

Response to the signal appears to be linear!

• Response (vo = vDS ) is also made of

a constant part (VDS ) and a signal response part (vds).

• Constant part of the response, VDS ,

is ONLY related to VGS , the constant part of the input (Q point on the transfer function of previous slide).

• i.e., if vgs = 0, then vds = 0
• The shape of the time varying portion
• f the response (vds) is similar to vgs.
• i.e., vds is proportional to the input

signal, vgs

• While overall response is non-linear,

response to the signal appears to be linear!

• F. Najmabadi, ECE65, Winter 2012

Although the overall response is non-linear, the transfer function for the signal is linear!

• F. Najmabadi, ECE65, Winter 2012

vgs vds vGS = VGS + vgs vDS = VDS + vds iD = ID + id Signal and response Constant: Bias Non-linear relationship among these parameters Linear relationship among these parameters

An Analogy: How much water is under the keel of a boat?

• Total Height, Hb = Bias (HB) + response to the added weight (hb)
• Complicated correlation between the total height, Hb , and the

weight of the boat.

• Simple correlation between hb and the added weight
• F. Najmabadi, ECE65, Winter 2012

Hb = HB Boat Pool Bias Added Weight (signal) Hb HB Bias + signal hb Response

An Analogy (2)

• Non-linear correlations among Bias + Signal: vGS , vDS , iD
• Simple (and linear) correlation between signal and response to the

signal: vgs , vds , id

• F. Najmabadi, ECE65, Winter 2012
• Bias: zero added weight & HB
• Bias + Signal: total weight & Hb
• Signal & response: added weight & hb
• Bias: VGS , VDS , ID
• Bias + Signal: vGS , vDS , iD
• Signal & response: vgs , vds , id

Added Weight (signal) Hb HB hb

Important Observations!

• Signal: We want the response of the circuit to this input.
• Bias: State of the system when there is no signal (current and

voltages in all elements).

• Bias is constant in time (may vary very slowly compared to the signal)
• Purpose of the bias is to ensure that MOS is in saturation at all times.
• Response of the circuit (and elements within) to the signal is

different than the response of the circuit and its elements to Bias (or to Bias + signal):

• Different transfer function for the circuit
• Different iv characteristics for elements, i.e. relationships among vgs ,

vds , id are different than relationships among vGS , vDS , iD .

• F. Najmabadi, ECE65, Winter 2012

Above observations & conclusions equally apply to a BJT in the active mode!

Transistor Amplifier Development

• F. Najmabadi, ECE65, Winter 2012

Bias & Signal

..... : ,...) ( , , , : MOS

r R R r R R D gs GS GS D DS GS

i I i v V v R v V v i v v + = + = + = ..... , : , , , : MOS

R R D D DS GS

I V R I V V ..... , : , , , : MOS

r r D d ds gs

i v R i v v

+

Bias Signal only = (Bias + Signal) - Bias

?

Issues in developing a transistor amplifier:

1. Establish a Bias point (bias is the state of the system when there is no signal).

• Stable and robust bias point should be resilient to variations in β,

µnCox (W/L),Vt , … due to temperature and/or manufacturing variability.

2. Find the iv characteristics of the elements for the signal (which can be different than their characteristics equation for bias).

• This will lead to different circuit configurations for bias versus signal:

Signal circuit

3. Compute circuit response to the signal & develop transistor amplifier circuits

• F. Najmabadi, ECE65, Winter 2012

Transistor Biasing

(Bias is the state of the circuit when there is no signal)

1. Purpose: BJT should be in active (or MOS should in saturation) at all times.

• Bias point impacts the small-signal parameters.
• Bias point impacts how large a signal can be amplified

2. Bias point should be resilient to variations in β, µnCox (W/L),Vt , … due to temperature and/or manufacturing variability.

• F. Najmabadi, ECE65, Winter 2012

BJT biasing with Base Voltage (Fixed Bias)

• F. Najmabadi, ECE65, Winter 2012

B D BB B BE B B BB

R V V I V R I V : KVL BE − = + = −

* Typically VBB = VCC in order to reduce the need for additional reference voltages.

) ( : KVL CE

D BB B C CC CE CE C C CC

V V R R V V V R I V − − = + = − β

B D BB B C

R V V I I − = = β β

• F. Najmabadi, ECE65, Winter 2012

Exercise 1: Find RC and RB such that BJT would be in active with IC = 25 mA, VCE = 5 V. (VCC = 15 V, Si BJT with β = 100 and VA = ∞).

Ω = + × = + = −

−

400 5 10 25 5 1 : KVL CE

3 C C CE C C

R R V R I

V 7 . 5 and since Active in is BJT

0 =

≥ = >

D CE C

V V I

mA 25 . / = = β

C B

I I k 2 . 57 7 . 10 25 . 5 1 : KVL BE

3

= + × = + = −

− B B BE B B

R R V R I

• F. Najmabadi, ECE65, Winter 2012

Exercise 2: Consider the circuit designed in Exercise 1 (RC = 400 , RB = 57.2 k, VCC = 15 V ). Find the operating point of BJT if β = 200.

mA 25 . 7 . 10 2 . 57 5 1 : KVL BE

3

= + × = + = −

B B BE B B

I I V R I

V 7 . and V, 7 . : Active in is BJT Assume ≥ > =

CE C BE

V I V

V 5 400 10 50 5 1 : KVL CE

3

− = + × × = + = −

− CE CE CE C C

V V V R I mA 50 = =

B C

I I β

BJT in saturation! Note, compared to Exercise 1:

• IB is the same.
• IC increased.
• VCE decreased.

Why biasing with base voltage (fixed bias) does not work?

• Changes in BJT β changes the bias point drastically.
• BJT can end up in saturation or in cut-off easily.
• In fixed bias, IB is set through
• BJT β then sets IC = β IB (IC changes with β ).
• CE circuit then sets VCE .
• But, requirements for BJT in active are on IC and VCE and NOT on IB
• IC > 0 , VCE > VD0
• To make bias point independent of changes in β, the bias circuit

should “set” IC and NOT IB !

• F. Najmabadi, ECE65, Winter 2012

B D BB B

R V V I − =

Biasing with Emitter Degeneration

• F. Najmabadi, ECE65, Winter 2012

      + + = − + + = −

E B E D BB E E BE B B BB

R R I V V R I V R I V 1 : KVL BE β

Requires a resistor in the emitter circuit!

E B

R R ) 1 ( : If + << β

E D BB E C E E D BB

R V V I I R I V V − ≈ ≈ ≈ −

Condition of means that the voltage drop across RB is small and the bias voltage VBB – VD0 appears across RE , setting IE ≈ IC .

E B

R R ) 1 ( + << β

Independent of β !

Emitter resistor provides negative feedback!

• F. Najmabadi, ECE65, Winter 2012

T BE V

V B E E BE B B BB

e I R I V R I V

/

∝ + + =

Independent of β !

Negative Feedback:

• If IC ≈ IE ↑ (because β ↑) , VBE ↓ IB ↓ IC ≈ IE ↓
• If IC ≈ IE ↓ (because β ↓) , VBE ↑ IB ↑ IC ≈ IE ↑

β BE -KVL BE junction BE -KVL BE junction β

• Requires a resistor in the emitter circuit.
• The bias voltage VBB – VD0 should appear across

RE to set IE ≈ IC : 1.

• We need to set to ensure

that this condition is always satisfied!

• 2. VBE ≈ VD0 . In reality, VBE = VD0 ± ∆VBE with

∆VBE ≈ 0.1 V

• We need to set or

Requirements for Biasing with Emitter Degeneration

• F. Najmabadi, ECE65, Winter 2012

E E B B BE BB

R I R I V V + = −

E B E E B B

R R R I R I ) 1 ( + << ⇒ << β ) 1 (

min E B

R R + << β V 1 ≥

E ER

I V 0.1 >>

E ER

I

Emitter Degeneration Bias with a voltage divider

• F. Najmabadi, ECE65, Winter 2012

CC BB B

V R R R V R R R × + = =

2 1 2 2 1

||

Real Circuit Voltage Divider

• F. Najmabadi, ECE65, Winter 2012

Exercise 3: Find the bias point of the BJT (Si BJT with β = 200 and VA = ∞).

mA 84 . 2 510 7 . ) 1 /( 10 03 . 5 2.22 2.22 : KVL BE

3

= + + + × = + + = −

E E E E E BE B B

I I I R I V R I β

V 7 . and V, 7 . : Active in is BJT Assume ≥ > =

CE C BE

V I V

V 0.7 V 10.7 510 10 84 . 2 10 10 82 . 2 15 5 1 : KVL CE

3 3 3

= > = × × + + × × = + + = −

− − D CE CE E E CE C C

V V V R I V R I V 22 . 2 15 k 34 k 9 . 5 k 9 . 5 k 03 . 5 k 34 || k 9 . 5 ||

2 1 2 2 1

= × + = × + = = = =

CC BB B

V R R R V R R R A 14.1 ) 1 /( mA 82 . 2 ) 1 /( µ β β β = + = = + × =

E B E C

I I I I

Notes:

• 1. We need to solve the complete BE-KVL

as we do not know if

• 2. β >> 1 is a good approximation that

reduces the amount of work. Answers using β >> 1 approximation:

) 1 (

E B

R R + << β V 10.7 A 14.2 mA, 2.84 = = ≈ ≈

CE B E C

V I I I µ

Step 1: Find RC and RE

k 2.0 k 3.0 k 1.0 : Choose = − = =

E C E

R R R

• F. Najmabadi, ECE65, Winter 2012

Exercise 4: Design a BJT bias circuit (emitter degeneration with voltage divider) such that IC = 2.5 mA and VCE = 7.5 V. (VCC = 15 V Si BJT with β ranging from 50 to 200 and VA = ∞).

k 3.0 5 . 7 ) ( 10 5 . 2 15 5 1 : KVL CE

3

= + + + × × = + + = −

− E C E C E E CE C C

R R R R R I V R I

Free to choose individual values RE & RC (we will see later that amplifier parameters sets the individual values) Circuit Prototype Check:

V 1 ≥

E ER

I V 1 5 . 2 10 10 5 . 2

3 3

≥ = × × =

− E ER

I

Step 2: Find RB and VBB Using relative error, ε = 10% Use largest RB (Will see later why)

• F. Najmabadi, ECE65, Winter 2012

Exercise 4 (Cont’d): Design a BJT bias circuit (emitter degeneration with voltage divider) such that IC = 25 mA and VCE = 5 V. (VCC = 15 V Si BJT with β ranging from 50 to 200 and VA = ∞).

k 5.1 k 5.1 ) 1 ( 0.1 ) 1 (

min min

= → = + ≤ → + <<

B E B E B

R R R R R β β V 20 . 3 10 10 2.5 0.7

3 3

= → × × + = + ≈ + + =

BB

• E

C D BB E E BE B B BB

V R I V V R I V R I V

Step 3: Find R1 and R2

213 . 15 3.20 k 10 . 5 ||

2 1 2 2 1 2 1 2 1

= = + = = + = = R R R V V R R R R R R R

CC BB B

k 6.4 k 23.9 213 . k 10 . 5

2 1

= = = R R

Step 4: Find commercial R values: RC = 2 k RE = 1 k R1 = 24 k R2 = 6.4 k

Why biasing with base voltage (fixed bias) does not work?

• Changes in BJT β changes the bias point drastically.
• BJT can end up in saturation or in cut-off easily.
• In fixed bias, IB is set through
• BJT β then sets IC = β IB (IC changes with β ).
• CE circuit then sets VCE .
• But, requirements for BJT in active are on IC and VCE and NOT on IB
• IC > 0 , VCE > VD0
• To make bias point independent of changes in β, the bias circuit

should “set” IC and NOT IB !

• F. Najmabadi, ECE65, Winter 2012

B D BB B

R V V I − =

Emitter-degeneration bias circuits

• F. Najmabadi, ECE65, Winter 2012

Basic Arrangement

E E BE B B BB

R I V R I V + + =

Bias with one power supply (voltage divider)

E E BE B B BB

R I V R I V + + =

Bias with two power supplies

E E BE B B EE

R I V R I V + + =

EE E E BE B B

V R I V R I − + + =

MOS bias with Gate Voltage

• This method is NOT desirable as µnCox (W/L) and Vt are not “well-

defined.” Bias point (i.e., ID and VDS) can change drastically due to temperature and/or manufacturing variability.

• See S&S Exercise 5.33 (S&S 5th Ed: Exercise 4.19): Changing Vt from 1 to

1.5 V leads to a 75% change in ID.

• F. Najmabadi, ECE65, Winter 2012

D D DD DS t GS

• x

n D

R I V V V V L W C I − = − =

2

) ( 5 . 0 µ

MOS bias with Source Degeneration (Resistor Rs provides negative feedback!)

• F. Najmabadi, ECE65, Winter 2012

Negative Feedback:

• If ID ↑ (because µnCox (W/L) ↑ or Vt ↓ ) VGS ↓ ID ↓
• If ID ↓ (because µnCox (W/L) ↓ or Vt ↑ ) VGS ↑ ID ↑

ID Eq. GS KVL GS KVL ID Eq.

• Feedback is most effective if

S G D D S G GS GS D S

R V I I R V V V I R / ≈ ⇒ = + − >>

2

) ( 5 .

t GS

• x

n D D S G GS

V V L W C I I R V V − = − = µ

Source-degeneration bias circuits

• F. Najmabadi, ECE65, Winter 2012

Basic Arrangement

S D GS G

R I V V + =

Bias with one power supply (voltage divider) Bias with two power supplies

SS S D GS

V R I V − + =

S D GS G

R I V V + =

S D GS SS

R I V V + =

• F. Najmabadi, ECE65, Winter 2012

Exercise 5: Find the bias point for Vt = 1 V and µnCox (W/L) = 1.0 mA/V2 (Ignore channel-width modulation).

Voltage divider (IG = 0)

V 7 15 ) 8 7 /( ) 7 ( = × + =

G

V V 1 6 5 7 ) 10 5 . ( 10 1 7 7 : KVL

• GS

5 .

2 2 3 4 2

= → = − + = × × + + = + + + = = =

− OV OV OV OV OV D S t OV D S GS G OV

• x

n D

V V V V V I R V V I R V V V L W C I µ V 5 V 10 15 15 : KVL

• DS

= − = = − = + =

S D DS D D D D D D

V V V I R V V I R mA 5 . / V 5 2 7 V 2 1 = = = − = − = = + =

S S D GS G S OV GS

R V I V V V V V

Exercise (impact of RS): Prove that if Vt = 1.5 V (50% change), ID = 0.455mA (9% change)

Biasing in ICs

• Resistors take too much space on the chip. So, biasing with emitter
• r source degeneration are NOT implemented in ICs.
• Recall that the goal of a good bias is to ensure that IC and VCE (or

ID and VDS for MOS) do not change. One can force IC (or ID for MOS) to be constant using a current source.

• F. Najmabadi, ECE65, Winter 2012

Current source forces IE = I Current source forces ID = I

BJT response to a current source

• F. Najmabadi, ECE65, Winter 2012

1) Current source forces:

I I I

E C

= ≈

3B) VE is set by BE-KVL

E BE B B

V V I R + + =

2) IB = IC / β 3A)

C C CC C

I R V V − =

4)

E C CE

V V V − =

MOS response to a current source

• F. Najmabadi, ECE65, Winter 2012

1) Current source forces:

I ID =

3B)

GS GS G S

V V V V − = − =

2) VGS is set by

2

) ( 5 .

t GS

• x

n D

V V L W C I − = µ

3A)

D D DD D

I R V V − =

4)

S D DS

V V V − =

Current Mirrors (or Current Steering circuits) are used as current sources for biasing ICs

• F. Najmabadi, ECE65, Winter 2012

Identical BJTs

• Qref is always in active since
• Identical BJTs and vBE,ref = vBE1
• BJTs will have the same iB and the

same iC (ignoring Early effect)

, , , D ref BE ref CE ref C

V V V i = = > β

C C B ref C ref

i i i i I 2 2 : KCL

,

+ = + = / 2 1 1

ref ref C

I I i I ≈ + = = β

• For the current mirror to work, Q1

should be in active:

1 1 D EE C CE

V V V V ≥ + =

• Since I1 = const. regardless of

VC1 , this is a current source!

An implementation of a BJT Current Mirror

• F. Najmabadi, ECE65, Winter 2012

R V V V I I V V I R V

D EE CC ref EE BE ref CC ref 1

: ) Q ( KVL

• BE

− + = ≈ − + =

• F. Najmabadi, ECE65, Winter 2012

Exercise 6: Find the bias point of Q2 (Si BJT with β = 100 and VA = ∞).

mA 4.65 mA 4.65 5 10 2 5

1 3

= ≈ = − + × =

ref ref BE ref

I I I V I

Current Mirror

V 1.165 7 . 10 5 . 46 10 10 10 10 : KVL

• BE2

2 1 2 6 3 2 2 2 3

− = = + + × × × = + + × =

− E C E E BE B

V V V V V I A 46.5 / mA 4.65

2 2 1 2 2

µ β ≈ = ≈ = ≈

C B E C

I I I I I V 7 . 1.56 V 1.56 165 . 1 10 65 . 4 10 5 10 5 : KVL

• CE2

2 2 3 3 2 2 2 2 3

= > = = − × × − = + + =

− D CE CE CE E CE C

V V V V V V I

Assume Q2 in active: Q2 in active! Check Q1 in active:

V 7 . 3.835 V 3.835 5 1.165 ) 5 (

1 1 1

= > = = + − = − − =

D CE C CE

V V V V

Examples of BJT current mirrors

• F. Najmabadi, ECE65, Winter 2012

PNP current Mirror

• One “reference” BJT feeds many current mirrors
• Integer multiple of Iref can be made (See Q3 & Q4)

MOS Current-Steering Circuit

• F. Najmabadi, ECE65, Winter 2012

An implementation of a MOS current steering circuit

• F. Najmabadi, ECE65, Winter 2012

The above quadratic equation gives VOV . I1 is then found from the MOS iD equation.

SS GS D DD ref OV ref

• x

n D ref

V v Ri V V L W C i I − + = = = : ) Q ( KVL

• GS

) / ( 5 .

2

µ ] [ ] ) / ( 5 . [

2

= + − − + + = + − − +

t DD SS OV OV ref

• x

n t DD SS OV D

V V V V V R L W C V V V V Ri µ

Examples of MOS current steering circuits

• F. Najmabadi, ECE65, Winter 2012
• One “reference” MOS feeds many current steering

circuits.

• Any value of Iref can be made (thus, current-

steering circuit instead of current-mirror)

( ) ( )ref

ref

L W L W I I / /

1 1 =

( ) ( )ref

ref

L W L W I I / /

2 2 =

PMOS current steering circuit

An implementation of current steering circuit to bias several transistors in an IC

• F. Najmabadi, ECE65, Winter 2012

Exercise: Compute I4/Iref