IEEE EMC Society Distinguished Lecturer Seminar: IEEE EMC Society - - PowerPoint PPT Presentation

IEEE EMC Society Distinguished Lecturer Seminar: IEEE EMC Society Distinguished Lecturer Seminar: IEEE EMC Society Distinguished Lecturer Seminar: Signal Integrity of TSV-Based 3D IC IEEE EMC Society Distinguished Lecturer Seminar: Signal Integrity of TSV-Based 3D IC

July 21 2010 July 21, 2010 Joungho Kim at KAIST joungho@ee kaist ac kr joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr

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Contents

1) Driving Forces of 3D Package and IC 2) Signal Integrity Design 3) N i C li I 3) Noise Coupling Issues 4) Noise Isolations 5) Summary

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3D Movie 3D Movie

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3D Housings 3D Housings

Sk L Sky Lounge Apartment Medical care Restaurant Fitness & Spa center Parking Fitness & Spa

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16GB Samsung NAND Flash, 8Gbx16 16GB Samsung NAND Flash, 8Gbx16

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Sharp, Morihiro Kada

3D Hamburger 3D Hamburger

SDRAM Di it l C Digital Core RF Analog

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Expected Market of 3D IC Expected Market of 3D IC

Heterogeneous integration “More than Moore”

Market Driving Forces of 3D IC

Performance driven

Co-integration of RF + logic + memory + sensors in a reduced space

Electrical performance ”Mid t ”

Logic

DRAM

Electrical performance

Interconnect speed and reduced parasitic power consumption

”Mid term” driver: > 2010

3D IC 3D IC

Optimum Market Optimum Market

MEMS RF- SiP

3D vs. “More Moore”

Can 3D be cheaper than going to the next lithography node?

Form factor driven Cost driven

Access Conditions Access Conditions

CIS SiP

Density

Achieving the highest

“Long term”

Flash

(NAND & NOR)

Source: “3D IC & TSV Report” Yole Development

driven driven

capacity / volume ratio

“Short term” driver: > 2008 Long term driver: > 2012

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Source: 3D IC & TSV Report , Yole Development

Technology Trend of 3D IC Technology Trend of 3D IC

* f IBM J RES & DEV VOL 52 NO 6 NOVEMBER 2008

O per cm2) 3D-I C integration

I/O: 0.4 - 10.0μm pitch 105 – 108 I/O per cm2 Wiring pitch: 45nm * ref: IBM J. RES. & DEV. VOL. 52 NO.6 NOVEMBER 2008, p555

tch, and ranges (I / O Si-on-Si package and chip stacking

Wiring pitch: 45nm

pitch, I / O pi tion density p g

I/O: 10-50μm pitch 103 - 106 I/O per cm2 Wiring pitch: 0.5μm

ive wiring p nterconnect

I/O: 200 μm pitch

Organic and ceramic package (SCM and MCM) Relati I / O in

I/O: 200-μm pitch 102 - 103 I/O per cm2 Wiring pitch: 25 - 200μm

2000 2010

Time Relative comparison of I / O densities for 3D silicon, 3D die stacking,

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8 Relative comparison of I / O densities for 3D silicon, 3D die stacking, and silicon packaging, for both ceramic and organic packaging

Core Technologies of 3D IC Core Technologies of 3D IC

Unified Unified Design/CAD Design/CAD

Attach Attachment nt TSV TSV Su Substrate Vi Via Ball Ball PCB PCB

Design/CAD Design/CAD Environment Environment and Test and Test Chip & SoC Chip & SoC Architecture and Architecture and Design Methodologies Design Methodologies 3D Thermal 3D Thermal & Reliability Analysis & Reliability Analysis And Design And Design

3D IC 3D IC 3D IC 3D IC

Design Methodologies Design Methodologies Methodologies Methodologies Low Cost Interposer Low Cost Interposer Chip Chip-to to-

• Wafer

Wafer p Process and Design Process and Design Technology Technology p Stacking & Bonding, Stacking & Bonding, TSV Technology TSV Technology

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Signal Integrity Design Issues in 3D IC Signal Integrity Design Issues in 3D IC

3D IC using TSV Signal Integrity II: Signal Integrity II: Crosstalk & Jitter Crosstalk & Jitter Signal Integrity I: Signal Integrity I: Loading Effect & Reflection Loading Effect & Reflection g (Through Silicon Via)

CIS

S21(Phase) [Degree]

• 40
• 30
• 20
• 10

( ) Frequency [GHz] 0.1 1 20 10 Solid line = model Symbol line = measurement Si Lvia Rvia C Cox Gsil Gsil Csil Csil Cvia_ox Cvia_ox Signal via Ground via Ground via Port 1 SiO2 Cvia_ox C Csil Cvia_ox Cvia_ox Cvia_ox Gsil Gsil Lvia Rvia Lvia Rvia Cvia_ox Cvia_ox Cox Csil

Logic

• Limitation of High Speed Signaling

by Capacitive Loading

• Impedance Mismatching, Reflection

Cox Port 2 Cox

• Crosstalk Between TSVs
• Die-to-Die Vertical Coupling
• Jitter by Inter-Symbol-Interference

Analog RF DRAM Si-Interposer

Power Integrity Power Integrity

EMI EMI

p DSP

Power Integrity Power Integrity

Power VSSN

Through-

Chi 4 Chip 5 Chip 6 Chip 7

Power Ground

Through wafer via

Chip 1 Chip 2 Chip 3 Chip 4

• Vertical Die-to-Die EMI Coupling
• Simultaneous Switching Noise caused

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Vertical Die to Die EMI Coupling

• RF Sensitivity Reduction by EMI
• EM Radiation Increase

Simultaneous Switching Noise caused by Insufficient Power

• High freq Noise Coupling & Transfer

10

Disadvantages of Wire Bonding Stacked Chip Package Disadvantages of Wire Bonding Stacked Chip Package

• Long Interconnection

Long RC Delays High Impedance for Power Distribution Network Hi h P C ti High Power Consumption Poor Heat Dissipation (Thick Substrate)

• Bonding Wire located in Chip Perimeter

Low Density Chip Wiring Limited Number of I/O Limited I/O Pitch Large Area Package

3D Stacked Chip Package

• Complex Interposer

Long Redistribution Interconnection Bonding Wire located in Interposer Periphery

with Wire Bonding

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Key Technology : TSV (Through Silicon Via) Key Technology : TSV (Through Silicon Via)

• Short Interconnection

Reduced RC Delays Low Impedance for Power Distribution Network

3rd Chip (Thinned Substrate)

Low Impedance for Power Distribution Network Low Power Consumption Heat Dissipation Through Via

Under fill Dielectric 2nd Chip (Thinned Substrate)

• No Space Limitation for Interconnection

Multi-level On-chip Interconnect Under fill Dielectric Substrate)

p

High Density Chip Wiring No Limitation of I/O Number No Limitation of I/O Pitch Small Area Package

On chip Interconnect Si-Substrate SiO2 1st Chip

S a ea ac age

3D TSV Stacked IC

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★ W hy does TSV Fam ily happy ^ ^ ?

Elevator !!

Happy TSV Fam ily~ ! Sad W ire-bonding Fam ily~ ! So fast! ♬ 4th Floor So tired T^T ! It takes too So fast! It’s awesome!!

♬

3rd Floor much energy !!

• Shorter distance !
• Lower loss of energy !

Stairs !!

T^T T0T

Stairs !!

2nd Floor 1st Floor

^^

^^

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10 chip stacked Package by KAIST 10 chip stacked Package by KAIST 10 9 8 7 6 5 4 3 2 1

55 μm TSV diameter

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150 μm Pitch

Background(1): High-frequency Channel Loss in TSV Background(1): High-frequency Channel Loss in TSV

G Significant high frequency signal loss occur at Signal Transmission Through TSV Cvia_ox Gsil

• Significant high-frequency signal loss occur at Signal Transmission Through TSV
• The signal loss through TSV is caused by substrate leakage and coupling

dB]

0.1μm

gnitude) [d S21(mag

SiO2 Ta Cu Si

Close up of through wafer via Frequency [GHz]

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Magnitude of S21

Background(2): Increased Channel Loss in Multi-Stack TSV Background(2): Increased Channel Loss in Multi-Stack TSV

• Signal loss increases substantially with number of stacks/TSVs

Th i l l h h TSV i d b b l k d li Increased Total Resistance Increased Total Capacitance (Slopes)

• The signal loss through TSV is caused by substrate leakage and coupling

10 2-Stack TSVs 8 9 10 5-Stack TSVs 5 6 7 10-Stacked TSVs 3 4 5 1 2

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A Through Silicon Via Structure on Double-sided Silicon Substrate A Through Silicon Via Structure on Double-sided Silicon Substrate

Underfill Metal (M1,M2) Bump Insulation layer Inter-metal Dielectric Double sided y

1111111111111

TSV Double-sided Silicon Substrate

Cinsulator GSi sub

Underfill Inter-metal Dielectric Bump Cu SiO2 Si

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Frequency-dependent Loss of Through Silicon Via Frequency-dependent Loss of Through Silicon Via

Frequency dependent term

• 1

B)

Ci

l t

GSi

b

• 3
• 2

loss (dB

Cinsulator GSi sub

• 4

Insertion Capacitive region Resistive region Cu SiO Si Leakage current

• 6
• 5

I Cu SiO2 Si Loss term 1 6 Frequency (GHz) 10 20 0.1

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Scalable Equivalent Circuit Model of a TSV Scalable Equivalent Circuit Model of a TSV

Signal Ground Structural Parameters TSV TSV TSV diameter : d TSV-to-TSV pitch : p SiO2 thickness : t

C C CBump Cinsulator Cinsulator

SiO2 thickness : t Height : h Bump diameter : D

Cinsulator Cinsulator C LTSV LTSV

Equations C (d h t)

GSi

b

CSi sub RTSV RTSV Cinsulator Cinsulator

B B

Cinsulator (d,h,t) CSi sub (d,h,p,t) CBump (p,D) G (d h p D)

Cinsulator Cinsulator GSi sub

Bump Bump

GSi sub (d,h,p,D) RTSV (d,h) LTSV (d,h,p)

CBump

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Analysis of a TSV Channel with Insulator Thickness of TSV Analysis of a TSV Channel with Insulator Thickness of TSV

CInsulator=1.6 pF

Insulator thickness of TSV (t)

Signal Ground

• 1
• 0.5

e (dB) CInsulator/2 CInsulator/2 CInsulator=2.6 pF C =7 8 pF Signal

Top

Ground

Top

Insulator thickness of TSV ↓

• 2
• 1.5

magnitude CInsulator=7.8 pF

• 3.5
• 3
• 2.5

S21

[A]

C /2 C /2

0.1 1 10 3.5 20

Frequency (GHz)

Equivalent circuit model ( t = 0.5um ) E i l t i it d l ( t 0 3 )

CInsulator/2 CInsulator/2 Leakage current Signal

Bottom

Ground

Bottom

Insulator thickness dominantly affects frequency dependent loss of a TSV channel

Equivalent circuit model ( t = 0.3um ) Equivalent circuit model ( t = 0.1um )

Leakage through silicon substrate dominantly increases due to lowered impedance with increased Cinsulator in region [A].

Leakage current

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Insulator thickness dominantly affects frequency dependent loss of a TSV channel in region [A].

20

Pitch between Signal & Ground TSV (p)

Analysis of a TSV Channel with Pitch between TSVs Analysis of a TSV Channel with Pitch between TSVs

0 5

Pitch between Signal & Ground TSV (p)

CSi sub=3.14 fF CUnderfill, IMD LTSV ↓ Signal

Top

Ground

Top

• 1.5
• 1
• 0.5

ude (dB) CSi sub=3.48 fF CSi sub L

Top Top

Pitch between TSVs ↓

• 2.5
• 2

21 magnitu CSi sub=4.26 fF GSi sub LTSV LTSV

[B] [C ]

0.1 1 10

• 3.5
• 3

20

S Frequency (GHz)

Equivalent circuit model ( p = 190um ) Equivalent circuit model ( p = 150um )

CUnderfill, Bottom Signal

Bottom

Ground

Bottom

Equivalent circuit model ( p = 100um )

Due to relative small capacitance, pitch affects frequency dependent loss of a TSV channel from region [B].

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From region [C], inductance effect becomes dominant. Pitch dominantly affects frequency dependent loss of a TSV channel in region [B].

Analysis of a TSV Channel with TSV Diameter Analysis of a TSV Channel with TSV Diameter

Via diameter of TSV (d)

CInsulator ↑ CSi sub ↑ LTSV ↓

• 0.5

CI

l t

CI

l t

CUnderfill, IMD Signal

Top

Ground

Top

Via diameter ↑

• 1.5
• 1

nitude (dB) CInsulator CInsulator CSi sub LTSV LTSV ↑

• 2.5
• 2

S21 magn The effect of decrease of pitch between TSVs GSi sub RTSV RTSV

[C ] [B] [A]

0.1 1 10

• 3.5
• 3

20

Frequency (GHz) CInsulator CInsulator C Signal Ground

B tt

Frequency (GHz)

Equivalent circuit model ( d = 32um ) Equivalent circuit model ( d = 20um ) Equivalent circuit model ( d = 10um )

CSi sub ↑

Signal Ground

CUnderfill, IMD

Bottom Bottom

Si sub ↑

C ↑

TSV TSV

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Via diameter affects frequency dependent loss of a TSV channel, dominantly in region [A] and [B].

22 CInsulator ↑

Analysis of a TSV Channel with Via Height of TSV Analysis of a TSV Channel with Via Height of TSV

Via height of TSV (h)

CInsulator ↑ CSi sub ↑ LTSV ↑ Signal

Top

Ground

Top

• 1
• 0.5

e (dB) CSi sub CInsulator CInsulator

Top Top

Via Height ↑

• 2
• 1.5

magnitude GSi sub LTSV R LTSV

[C ] [B] [A]

• 3 5
• 3
• 2.5

S21 CInsulator CInsulator RTSV RTSV

]

0.1 1 10

• 3.5

20

Frequency (GHz)

Equivalent circuit model ( h = 110um )

CSi sub ↑ Signal

Bottom

Ground

Bottom

LTSV ↑

Equivalent circuit model ( h = 80um ) Equivalent circuit model ( h = 50um )

CSi sub ↑ CInsulator ↑

Signal TSV Ground TSV

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Via height affects frequency dependent loss of a TSV channel in all frequency ranges.

Inter-symbol Interference (ISI) by Channel Loss Inter-symbol Interference (ISI) by Channel Loss

• Inter

Inter-

• symbol Interference

symbol Interference is the interference between adjacent pulses

• f a data
• The channel BW Limit degrades the signal quality

The channel BW Limit degrades the signal quality

• It depends on

It depends on line line-

• length

length, , data rate data rate and and sub. materials

• sub. materials on PCB
• n PCB

Short Channel Long Channel

[mV] 400 500 600 400 500 600 [mV]

Short Channel Long Channel

Voltage 100 200 300 100 200 300 Voltage

40 % reduction

0000 0110110

Time [ns]

• 100

15 5 10

– Channel Length = 40 cm – Channel Length = 10 cm

• 100

Time [ns] 15 5 10

Channel Length 40 cm – 3 Gbps – FR4 (Loss Tangent = 0.03) Channel Length 10 cm – 3 Gbps – FR4 (Loss Tangent = 0.03) [ ISI effect due to line-length ]

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Inter-Symbol Interference at the TSV Equalizer Inter-Symbol Interference at the TSV Equalizer

0 25 0.25

(V)

[dB]

Voltage

agnitude) [

Ti ( )

100 80 20 40 60

• 0.25

S21(ma

Time (ps)

Frequency [GHz] Magnitude of S21

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The Proposed TSV Equalizer using an Ohmic Contact The Proposed TSV Equalizer using an Ohmic Contact

Ohmic contact

(Al/n+ type) Signal TSV Ground TSV ( yp ) n-type Silicon n+ high doped Silicon Silicon Substrate

Bump Bump

We intentionally made leakage by using an Ohmic contact resulting in DC attenuation between signal and ground TSV

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resulting in DC attenuation between signal and ground TSV.

26

Frequency Domain Simulation-based Verification of the TSV Equalizer Performance Frequency Domain Simulation-based Verification of the TSV Equalizer Performance

Insertion loss of 8 TSVs without TSV equalizer

• 2

s (dB)

• 4.8 dB

without TSV equalizer

• 4

ertion loss

• 4.5

0 7dB 1 dB

• 3.8 dB
• 6

Inse Flattened from DC to 10GHz (Nyquist frequency of 20Gbps) 0.7dB 1 dB

0.1 1 10

• 8

F (GH )

20

Insertion loss of 8 TSVs with TSV equalizer Frequency(GHz)

• We successfully flattened frequency dependent loss by 3.8 dB

by using TSV Equalizer

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by using TSV Equalizer.

Time Domain Simulation-based Verification of the TSV Equalizer Performance Time Domain Simulation-based Verification of the TSV Equalizer Performance

0 25 0 25 0.25

(V)

0.25

Pk-pk jitter : 16 ps

(V) Voltage Voltage Ti ( )

100 80 20 40 60

• 0.25

Ti ( )

100 80 20 40 60

• 0.25

Eye opening: 100mV

Time (ps)

• We successfully achieved normalized pk pk jitter and eye opening

Time (ps)

• We successfully achieved normalized pk-pk jitter and eye-opening,

32% and 20%, meanwhile the unequalized eye is completely closed.

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Time-Domain Measurement Results Time-Domain Measurement Results

• Measured Eye-diagrams of a TSV channel

Eye-opening : 904 mV = 90.4% Vin (1V) 1 1 1 Eye-opening : 720 mV = 72% Vin (1V) Eye-opening : 685 mV = 68.5% Vin (1V) Pk-pk jitter : 50 ps = 0 5% UI Voltage (V) Voltage (V) Voltage (V) Pk-pk jitter : 12.5 ps = 1 25% UI Pk-pk jitter : 27.8 ps = 18 9% UI 0.5 0.5 0.5 0.5% UI Time (nsec) 6 10 8 2 4 1.25% UI 18.9% UI Time (nsec) Time (psec) 0.6 1 0.8 0.2 0.4 120 200 160 40 80

• Data rate : 100 Mb/s
• Data Pattern : PRBS 211-1,
• Data rate : 1 Gb/s
• Data Pattern : PRBS 211-1,
• Data rate : 5 Gb/s
• Data Pattern : PRBS 211-1,
• Source amplitude : 1 V
• Source amplitude : 1 V
• Source amplitude : 1 V

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Coupling Issues in Stacked Dies using TSV Coupling Issues in Stacked Dies using TSV

Bonding Bonding Adhesive P-Substrate 3rd Chip Bonding Adhesive Adhesive I nductor N-Well N+ P+ P+ P+ N+ N+ P+ N+ N+ P+ N+ N-Well N+ N-Well TSV TSV Metal to Metal TSV TSV N Well P-Substrate N Well N-Well 2nd Chip I nductor 2 TSV to Active Circuit Coupling 3 Coupling N W ll N+ P+ P+ P+ N+ N+ P+ N+ N+ P+ N+ N W ll N+ N W ll Coupling 1 TSV to TSV Coupling TSV TSV N-Well P-Substrate N-Well N-Well 1st Chip < CROSSSECTI ONAL VI EW >

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Measurement Result of Coupling between TSVs Measurement Result of Coupling between TSVs

• 10

20

G S

• 20
• 30

G S

efficient [dB]

Gsi

Csi + Cparasitics

• 40
• 50

Measurement

< Top view>

G S

Coupling co

Cox

Freq [GHz]

• 60

0.1 1 10 20

Freq [GHz]

Model

p

Cm

Freq [GHz] Freq [GHz]

M

Gsi Csi R Cox Cp1

• Analytic model of coupling between TSVs shows good

agreement with measurement result

M

L

g

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• 31-

< Equivalent circuit model of coupled TSV>

Shielding Methods for TSV Coupling

1) Re-design of TSV materials and dimensions 2) Separation 3) G d Ri 3) Guard Ring 4) GND Shield TSV 5) Metal Ring

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Shielding E ffect Measurement – (1) Metal Ring Shielding E ffect Measurement – (1) Metal Ring

• 10

G

ficient [dB]

• 20
• 30

G

Coupling coeff

• 40

w/ o metal ring

G S

< Top view> C

• 50
• 60

0 1 1 10 20

w/ o metal ring w/ metal ring Cm

< Top view> 0.1 1 10 20 Freq [GHz]

• Metal ring has shielding effect only in high frequency

M

Gsi Csi R Cox Cp1

because it blocks coupling in IMD layer

M

L

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• 33-

< Equivalent circuit model of coupled TSV>

Shielding E ffect Measurement– (2) Guard Ring Shielding E ffect Measurement– (2) Guard Ring

• 10

G

• 20
• 30

G

ficient [dB]

• 40

w/ o guard ring

G S

< Top view> Coupling coeff

• 50
• 60

0 1 1 10 20

w/ o guard ring w/ guard ring Cm

< Top view> C 0.1 1 10 20 Freq [GHz]

• Guard ring has good shielding effect in every frequency

M

Gsi Csi R Cox Cp1

range because guard ring structure can partly block substrate coupling between TSVs

• Main factor of coupling between TSVs is silicon substrate

M

L

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• 34-
• Main factor of coupling between TSVs is silicon substrate

< Equivalent circuit model of coupled TSV>

Shielding E ffect Measurement– (3) Guard Ring + Metal Ring Shielding E ffect Measurement– (3) Guard Ring + Metal Ring

• 10

G

• 20
• 30

G

ficient [dB]

• 40

w/ o guard ring

G S

< Top view> Coupling coeff

• 50
• 60

0 1 1 10 2x10

w/ guard ring w/ guard ring + metal ring Cm

< Top view> C 0.1 1 10 2x10 Freq [GHz]

• Metal ring structure with guard ring can further decrease

M

Gsi Csi R Cox Cp1

coupling between TSVs

M

L

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• 35-

< Equivalent circuit model of coupled TSV>

Measurement E nvironments for Model Verification Measurement E nvironments for Model Verification

Vector Network Analyzer (VNA) Measurement instrument : Agilent Technology PNA-L N5230A g gy Frequency range : 10MHz ~ 20GHz Frequency sweep : log scale, 1601 point microprobe : GGB industries inc. 40A-GS- 250-P Port1 Port2 microprobe microprobe Port2

FOX FOX FOX ILD/IMD

RDL RDL

FOX FOX P+ P+ FOX P+

TSV substrate contact [ C ti l i f t t l ] silicon substrate

Open

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Designed Test Sample Images Designed Test Sample Images

RDL(Redistribution layer) RDL(Redistribution layer)

Dummy skip layer

G G

IMD / ILD

Contact Dummy skip layer

coupling IMD / ILD Silicon substrate

TSV Contact

S S

[ Top view of test sample ] TSV Contact [ Cross sectional ie

• f test sample ]

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[ Cross sectional view of test sample ]

Analysis of Noise Coupling based on the 3D TLM Model Analysis of Noise Coupling based on the 3D TLM Model

conta ILD/IM D A B C 35

• 30

cient [dB] ct TSV CTSV Rsub Csub

• 40
• 35

Silicon resistance dominant Silicon capacitance dominant pling coeffi silicon substrate Di t b t t t d TSV

• 50
• 45

TSV SiO2 capacitance d i t Coup Distance between contact and TSV : 100 μm Substrate height : 100 μm TSV diameter : 30 μm

• 55

dominant TSV diameter : 30 μm TSV SiO2 thickness : 0.5 μm 10M 100M 1G 10G

• 60

Frequency [GHz]

• Coupling can be divided into 3 regions
• Coupling can be divided into 3-regions
• In region A, B, and C TSV SiO2 capacitance , silicon resistance, silicon

capacitance is the dominant factor to the coupling

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capacitance is the dominant factor to the coupling

Substrate contact to TSV Coupling 3D TLM Model Verification by Measurement – with Distance Variation Substrate contact to TSV Coupling 3D TLM Model Verification by Measurement – with Distance Variation

Distance Increases 50 um

• 10

] 100 um 200 um

• 20

icient [dB]

• 30

pling coeffi Measurement The proposed model

• 40

Coup

• Proposed model’s coupling coefficient estimation is less than measurement

p p 10M 100M 1G 10G

• 50

Frequency [Hz]

• Proposed model’s coupling coefficient estimation is less than measurement
• ver 1GHz
• But model follows same tendency as the distance increases

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• But model follows same tendency as the distance increases

Analysis of Noise Coupling based on the 3D TLM Model – with TSV SiO

2 Thickness Variation

Analysis of Noise Coupling based on the 3D TLM Model – with TSV SiO

2 Thickness Variation conta

• 20

A B C ILD/IM D ct TSV CTSV Rsub Csub cient [dB]

• 30

tox_TS

V

CTS

V

Coupli ng silicon substrate Di t b t t t d TSV TSV SiO2 thickness (tox TSV) pling coeffi

• 40

Coupling coefficient d Distance between contact and TSV : 100 μm Substrate height : 100 μm TSV diameter : 30 μm Coup

• 50

tox_TSV = 0.3um tox_TSV = 0.5um tox_TSV = 0.7um decreases 10M 100M 1G 10G TSV diameter : 30 μm TSV SiO2 thickness : 0.3, 0.5, 0.7 μm Substrate conductivity : 10S/m

• 60

Frequency [GHz]

• TSV SiO thickness determine the coupling coefficient in the region A
• TSV SiO2 thickness determine the coupling coefficient in the region A
• If we increases TSV SiO2 thickness, coupling coefficient decreases in the

region A

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region A

Analysis of Noise Coupling based on the 3D TLM Model – with Silicon substrate Height Variation (1) Analysis of Noise Coupling based on the 3D TLM Model – with Silicon substrate Height Variation (1)

conta

• 20

A B C ILD/IM D h C ct TSV CTSV Rsub Csub height (h) cient [dB]

• 30

h CTS

V

, Rsub Coupli ng , Csub silicon substrate Di t b t t t d TSV pling coeffi

• 40

Coupling coefficient increases Distance between contact and TSV : 100 μm Substrate height : 30, 70, 100 μm TSV diameter : 30 μm Coup h = 30um h = 70um h = 100um

• 50

10M 100M 1G 10G TSV diameter : 30 μm TSV SiO2 thickness : 0.3 μm Substrate conductivity : 10S/m

• 60

Frequency [GHz]

• If silicon substrate height decreases all component value is changed
• If silicon substrate height decreases, all component value is changed
• At the whole frequency, the coupling coefficient increases as silicon substrate

height increases

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height increases

Analysis of Guard-ring based on the 3D TLM Model – with Guard-ring Location Variation Analysis of Guard-ring based on the 3D TLM Model – with Guard-ring Location Variation

• 30

conta guard- ring A B C C’

• 40

cient [dB] ct TSV A’ B’ C’

• 50

pling coeffi Distance between contact and TSV : 100 μm silicon substrate

• 60

Coup 100 μm Substrate height : 100 μm TSV diameter : 30 μm TSV SiO2 thickness : 0.5 μm w/o guard-ring with guard-ring around TSV with guard-ring around contac 10M 100M 1G 10G

• 70

Frequency [Hz]

2

μ Guard-ring distance from contact : 10 μm Guard-ring width : 10 μm

• Guard ring around contact shows more isolation effect compared to guard ring
• Guard-ring around contact shows more isolation effect compared to guard-ring

around TSV

• Guard ring around contact does not have frequency dependent isolation effect

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• Guard-ring around contact does not have frequency dependent isolation effect

PLL Coupling Simulation E nvironment PLL Coupling Simulation E nvironment

PFD CP VCO LPF

½ ½ ½ ½ ½ ½

Output

noise source Is assumed as square wave metal ILD / IMD G ½ ½ ½ ½ ½ [ PLL ] [ Active circuit noise ] square wave (500mV , 305MHz ) contact metal TSV S G S ili b TSV silicon substrate [ PLL external clock ] [ Active circuit to TSV coupling model ]

• Contact to TSV coupling model was proposed and verified in the previous
• Contact to TSV coupling model was proposed and verified in the previous

chapter

• HSPICE simulation was performed using the contact to TSV coupling model

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43 43

• HSPICE simulation was performed using the contact to TSV coupling model

and PLL schematic

Substrate Noise Coupling to TSV Substrate Noise Coupling to TSV

• 20

20 dB] 305 MHz 305*3 MHz 305*5 MHz

• 30
• 40
• 20

efficient and TSV [d ge (dBV) 305 5 MHz 305*7 MHz

...

305*9 MHz

• 40
• 60
• upling co

en contact a

• ise voltag
• 50
• 80

Co betwee No

• 305MHz square wave noise is coupled to TSV by the coupling coefficient
• 60
• 100

10M 100M 1G 10G Frequency [Hz]

• 305MHz square wave noise is coupled to TSV by the coupling coefficient
• Up to 9th harmonic frequency, coupling coefficient is almost constant

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44 44

PLL Phase Noise Degradation due to Active Circuit to TSV Coupling PLL Phase Noise Degradation due to Active Circuit to TSV Coupling

60

• 50

PLL

Output Externa l

No noise 305MHz, 500mV (dBc/Hz)

• 70
• 60

Clock

coupled noise 2nd harmonic of 3rd harmonic of 2.4GHz output Phase noise spur generated due to TSV coupled noise ase Noise

• 80

2 harmonic of 2.4GHz output Pha

• 90
• PLL phase noise shows spurs at 5MHz due to coupled 305MHz noise

1M 5G Frequency [Hz] 10M 100M 1G

• 100
• PLL phase noise shows spurs at 5MHz due to coupled 305MHz noise
• PLL phase noise spur at 75MHz, 2.4GHz, 4.8GHz is due to circuit design

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Substrate Noise Coupling to TSV Substrate Noise Coupling to TSV

• 20

20 dB] 305 MHz 305*3 MHz 305*5 MHz w/o guard-ring Guard-ring around TSV

• 30
• 40
• 20

efficient and TSV [d ge (dBV) 305 5 MHz 305*7 MHz

...

305*9 MHz

• 40
• 60
• upling co

en contact a

• ise voltag

Guard-ring around TSV

• 50
• 80

Co betwee No

• Guard ring around TSV decreased coupling coefficient
• 60
• 100

10M 100M 1G 10G Frequency [Hz]

• Guard-ring around TSV decreased coupling coefficient
• PLL coupled noise also decreased by the guard-ring around TSV

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PLL Phase Noise Degradation due to Active Circuit to TSV Coupling PLL Phase Noise Degradation due to Active Circuit to TSV Coupling

60

• 50

PLL

Output Externa l

w/o guard-ring Guard-ring around TSV (dBc/Hz)

• 70
• 60

Clock

Phase noise decreased ~4dBc/Hz 2nd harmonic of 3rd harmonic of 2.4GHz output ase Noise

• 80

2 harmonic of 2.4GHz output Pha

• 90
• PLL phase noise spur at 5 MHz decreased by the guard ring

1M 5G Frequency [Hz] 10M 100M 1G

• 100
• PLL phase noise spur at 5 MHz decreased by the guard-ring
• Guard-ring around TSV can improve coupling degraded circuit performance

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BE R Calculation in Mixed-Signal System Model BE R Calculation in Mixed-Signal System Model

tr T BER teste r

data from RX raw data from TX data from RX raw data 1

r

f t π =

• 20dB/dec
• 40dB/dec

ctrum [dBm]

Coupling coefficient

bit error occurs frequency 3 5 7 9 Harmonic number Spec

Coupling coefficien

Generated noise

Digital Baseband (BER tester) coefficien t

Transmitte r of RF Signal

Receiver RF signal

RF signal from digital clock

noise tester)

Raw Data

Delay

Amp Signal g

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Dimension Region with Coupled TSV Parameters Dimension Region with Coupled TSV Parameters

50 um

1

BER Constant BER curve

d = 1 d = 1 ~ 50um ~ 50um

30 um

3x10 3x10-1

• 1

r

hTSV

TSV =

= 30um ~ 30um ~ 200um 200um p = 200um p = 200um tox

• x = 0.5um

= 0.5um

10 um 20 um

2x10 2x10-1

• 1

V diameter

5 um

10 10-1

• 1

TSV

Dimension region for acceptable BER 30 um 50 um 70 um 100 um 150 um 200 um 1 um

Silicon thickness

for acceptable BER

• In certain digital application, dimension region of TSV design parameters for

acceptable BER can be obtained from the modeling of coupled TSVs Silicon thickness

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Dimension Region with Coupled RDL Parameters Dimension Region with Coupled RDL Parameters

1

BER 200 um Constant BER curve

3x10 3x10-1

• 1

150 um

pace

Dimension region for acceptable BER

2x10 2x10-1

• 1

60 um 100 um

to-edge sp

10 10-1

• 1

40 um

Edge-t

s = 20 ~100 um s = 20 ~100 um l = 100 l = 100 ~500 um ~500 um w = w = 2 20um t = t = 1 1um

50 um 70 um 100 um 150 um 200 um 300 um

Coupled length

20 um

Coupled length

• In certain digital application, dimension region of RDL interconnects design

parameters for acceptable BER can be obtained from the modeling of coupled RDL

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50 50 p p g p interconnects

Dimension Region with Coupled TSV Parameters with Guard Ring Dimension Region with Coupled TSV Parameters with Guard Ring

1

50 um BER Constant BER curve

d = 1 d = 1 ~ 50um ~ 50um 3x10 3x10-1

• 1

30 um

r

hTSV

TSV =

= 30um ~ 30um ~ 200um 200um p = 200um p = 200um tox

• x = 0.5um

= 0.5um 2x10 2x10-1

• 1

10 um 20 um

V diameter

I d di i

10 10-1

• 1

5 um

TSV

Increased dimension region for acceptable BER 30 um 50 um 70 um 100 um 150 um 200 um 1 um

Silicon thickness

• By applying guard ring structure, dimension region for acceptable BER is

significantly increased Silicon thickness

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• Target BER can be satisfied within realizable dimensions

Vertical Coupling of DDR3 to ZigBee Transceiver Vertical Coupling of DDR3 to ZigBee Transceiver

Zigbee Tranceiver

VDD

Differential

Guardring N+ P+ P+ VCO of ZigBee Transceiver 2nd Chip

Die to Die

Differential Spiral Inductor

P+ N+ N+ P+ N+ N-Well N+ N Well TSV

Die-to-Die Vertical Coupling

DDR 3 N-Well N-Well 1st Chip TSV

DDR3

20dB/decade tude Pi*Tr 1 ㅡ Tr T

www.micron.co

40dB/decad e Amplit 1 F

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m

3 5 7 9 T 1 ㅡ Frequenc y

E xperimental Verification of Proposed Model (Line Type Clock Tree to Two Turn Spiral Inductor) E xperimental Verification of Proposed Model (Line Type Clock Tree to Two Turn Spiral Inductor)

60

C

60

2 Turn

e [dBΩ]

20 40

C Clock L Clock L

Inductor

L

Voltage Tr

20 40 Z =Clock Tree Impedance

Impedance

• 60
• 40
• 20

Inductor

ransfer Rat

• 60
• 40
• 20

L Inductor L

Clock

L M

Z21/Z11=V2/V1 Z21=Transfer Impedance Z11=Clock Tree Impedance Measurement

• 120
• 100
• 80

io [dB]

• 120
• 100
• 80

L

Inductor

C Clock L M

M

C epoxy R,C csub

Frequency[Hz]

0.1G 1G 10G 20G

• Before clock tree resonance, voltage transfer ratio is determined by Cclock and Linductor.
• After clock tree resonance, voltage transfer ratio is determined by Lclock and Linductor.

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53

Investigation of Vertical Coupling E ffect on VCO Spur Investigation of Vertical Coupling E ffect on VCO Spur

Clock spectrum (before vertical

V V /I V /I V Z Z A 1

1 2 1 1 1 2 11 21

= = =

dBV]

Voltag

20 20

2.4 GHz

Voltage Transfer Ratio p ( coupling)

)dB 1 20log( )dB 20log(V )dB 20log(V )dB A 1 * 20log(V V /I V Z A

1 2 1 1 1 1 11

+ =

Spectrum [d

e Transfer R

• 60
• 40
• 20

High-frequency Multiplicative Noise )dB 20log(V )dB A 20log( )dB 20log(V

2 1

= +

Clock

Ratio [dB]

• 120
• 100
• 80

0 1G 1G 10G 20G

[dBm]

20

Frequency(Hz)

0.1G 1G 10G 20G

• Main mechanism of spur

ti i hi h f

ut Spectrum

• 40
• 20

2.4 GHz generation is high-frequency multiplicative noise

• To reduce the spur at 10MHz offset

VCO Outpu

100

• 80
• 60

VCO Output Spectrum (after vertical coupling) VCO Output Spectrum (before vertical coupling)

from center frequency, design guide has to be proposed.

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Frequency(GHz)

2.38 2.4 2.42 2.44

• 100

Investigation of Design Guide for Spur Reduction (E poxy Thickness) Investigation of Design Guide for Spur Reduction (E poxy Thickness)

Clock spectrum (before vertical

Port 2 dBV]

Voltag

20 20 Voltage Transfer Ratio p ( coupling) Spiral Inductor Chip 90um

Spectrum [d

e Transfer R

• 60
• 40
• 20

Port 1

20um 80um

Clock

Ratio [dB]

• 120
• 100
• 80

0 1G 1G 10G 20G

Clock Tree Chip

[dBm]

20

Frequency(Hz)

0.1G 1G 10G 20G

• Spurs at 5MHz and 10MHz offset

f t f ti f th

ut Spectrum

• 40
• 20

from center frequency satisfy the spur spec of ZigBee system.

• Increasing epoxy thickness is

VCO Outpu

100

• 80
• 60

VCO Output Spectrum (after vertical coupling) VCO Output Spectrum (before vertical coupling)

highly effective for spur reduction.

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Frequency(GHz)

2.38 2.4 2.42 2.44

• 100

Summary

• TSV is the most critical interconnection structure in 3D IC.
• TSV can cause significant channel loss for high-speed signaling.

E li ifi I/O h d d t t l

• Equalizer or specific I/O schemes are needed to support low power

and high-speed data transmissions.

• Crosstalk and coupling between TSV and active circuit need to be

considered when designing the TSV arrangement configurations.

• Shielding structures are needed to reduce the TSV crosstalks and noise

couplings. couplings.

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