Power Integrity of SiP (System In Package) Power Integrity of SiP - - PowerPoint PPT Presentation

IEEE EMC Society Distinguished Lecturer Seminar: IEEE EMC Society Distinguished Lecturer Seminar: IEEE EMC Society Distinguished Lecturer Seminar:

Power Integrity of SiP (System In Package)

IEEE EMC Society Distinguished Lecturer Seminar:

Power Integrity of SiP (System In Package)

July 21 2010 July 21, 2010 Joungho Kim at KAIST joungho@ee kaist ac kr joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr

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Contents

I. Needs of SiP II. Power Integrity of SiP III PDN D i Ch ll i SiP III. PDN Design Challenges in SiP IV. Embedded decoupling capacitor and EBG structures V. PDN Isolation in SiP design VI PDN i li ff t Mi LNA d O A VI. PDN noise coupling effects on Mixer, LNA, and OpAmp VI. SSN Free 3D Clock Distribution Network VII. Power Integrity of TSV based 3D SiP

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• VIII. Conclusion

Ubiquitous Mobile Life Ubiquitous Mobile Life

Physical World Mobile Platform

Player Wired

Computing Communication

Brain Wireless

Sensing/ Cognition/ I dentification Entertainment

T l h Product

Entertainment Medical/ Welfare service

network

Telephony I nternet Robot Auto-mobile

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Auto mobile

3D Convergence System In Package 3D Convergence System In Package

3D Memory Multi-core 3D Memory Stack Multi-core Processor RF Transmitter/ Receiver

Filter Antenna

SRAM DRAM Flash Receiver

Embedded de-cap Termination Resistor EBG Structure

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Advantages of SiP approach Advantages of SiP approach

□ֺSmall form factor □ֺ Fast time to market □ֺ Inhomogeneous device integration □ g g □ֺ Integration of passive devices, filters, and antenna □ֺ Suitable for RF mobile communication systems □ֺ Low cost

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5

Power Supply Current Path Power Supply Current Path

Chip Ball Grid Array Package Low Inductance Capacitor on Package Discrete Decoupling Capacitor on PCB Bulk Capacitor Ball Bonding

VRM

Ground Power Wi B ll P k PCB Wire Bonding Ball Bonding Package P/G Network PCB P/G Network Chip VRM ΔI Decoupling Capacitor On Package Decoupling Capacitor On PCB Bulk Capacitor Near VRM Decoupling Capacitor On Chip

Low impedance path of current-flow at high frequency. Screen out large inductance.

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Simultaneous Switching Noise (SSN) Simultaneous Switching Noise (SSN)

ΔI=ΔI1+ ΔΙ2+ ΔIn

V=VCC+ΔV

ΔI1 ΔI2 ΔIn ΔI=ΔI1+ ΔΙ2+ …ΔIn

L Common Power Supply

H L H L H L 1 2 n

L

Parasitic Inductance (due to Pins, Bond-wire, etc.)

Common Ground Chip Simultaneous Switching Noise (SSN) : ΔV = L ΔI Δt

Increase of Maximum Power (Current) Increase of Clock Frequency

SSN caused by simultaneous switching output buffers

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Problems caused by SSN

• Voltage margin reduction
• Logic failure

N i li t iti i it (RF d l i it )

• Noise coupling to sensitive circuits (RF and analog circuits)
• Circuit reliability degradation (S/N, sensitivity)
• Signal integrity degradation ( eye, jitter)

El t ti di ti

• Electromagnetic radiation

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Inductive Impedance of PDN in SiP Inductive Impedance of PDN in SiP

LPKG,wire LPKG,trace LPKG,via LPCB,decap S G

PKG,via

LPKG,ball G P LP/G plane LPCB,via S

Ltotlal = LPKG,wire+ LPKG,trace+ LPKG,via+ LPKG,ball+ LPCB,via+ LP/G plane+ LPCB,decap

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Reduction of PDN Inductance

• Locate as close as possible
• Reduce length of interconnect

g

• Wider, planar interconnect
• Ground/return current path as close as possible, minimal loop size
• Choose low ESL decoupling capacitors

Choose low ESL decoupling capacitors

• On chip decap > on-package decap > on-PCB decap
• Thinner PCB and package substrate
• Provide multiple paths (via pin wire decoupling capacitors)

Provide multiple paths (via, pin, wire, decoupling capacitors)

• Choose advanced package

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• Cost balance needed

Power/Ground Network Impedance Power/Ground Network Impedance

Actual pedance Actual Impedance P/G Imp Ideal Impedance Frequency [log] kHz MHz GHz THz

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Frequency Dependent Functions of Discrete Decoupling Capacitor Frequency Dependent Functions of Discrete Decoupling Capacitor

e

Chip Decoupling Capacitor VRM

j L j j L j ω < ω

mpedance

Power Ground

DECAP DECAP VRM VRM

C L j C L j ω − ω < ω − ω

Network I

Capacitance given by Discrete Decoupling Capacitors Capacitance by Power/Ground Plane

r/Ground N Power

Inductance by VRM or Inductance given by

• ESL of Discrete Capacitor

Inductance by Power/Ground Plane

MH GHz

Frequency

ESL of Bulk Capacitor

• Mount Pad
• Power/Ground Traces
• Power/Ground Via

Power/Ground Plane

KH

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12 MHz GHz KHz

Frequency Dependent Functions of Discrete Decoupling Capacitor Frequency Dependent Functions of Discrete Decoupling Capacitor

e

VRM VRM DECAP DECAP

C j L j C j L j ω ω ω ω − < −

Chip Decoupling Capacitor VRM

mpedance

V C PLANE PLANE DECAP DECAP

C j L j C j L j ω ω ω ω − < −

Power Ground

Network I

Capacitance given by Capacitance given by Discrete Decoupling Capacitors Discrete Decoupling Capacitors Capacitance by Power/Ground Plane

r/Ground N Power

Inductance by VRM or Inductance given by

• ESL of Discrete Capacitor

Inductance by Power/Ground Plane

MH GHz

Frequency

ESL of Bulk Capacitor

• Mount Pad
• Power/Ground Traces
• Power/Ground Via

Power/Ground Plane

KH

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13 MHz GHz KHz

Good Power Distribution Network Good Power Distribution Network

Decoupling Capacitor Battery p Voltage regulator Power Power plane on PCB Package Device Power trace on PCB Wire- bond

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Low Impedance Water Pipe Low Impedance Water Pipe

Resistive Pipe Inductive Pipe

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Inductive Pipe

What happens if power distribution network is bad? What happens if power distribution network is bad?

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What happens if power distribution network is Good? What happens if power distribution network is Good?

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Impedance Property of Chip-Package-PCB Hierarchical PDN Impedance Property of Chip-Package-PCB Hierarchical PDN

thm) Interaction Interaction nce (Logari Impedan Frequency (Logarithm) 10MHz 100MHz 1GHz 10GHz

Advantage and application of PDN analysis in frequency domain Advantage and application of PDN analysis in frequency domain

• Intuitive analysis
• Easy to control impedance property

Need for hierarchical PDN simulation

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• Interactions between different level PDNs generate high impedance peak.

Case Study : Design of P/G Ring and Bonding Wire for 40Gbps PKG Case Study : Design of P/G Ring and Bonding Wire for 40Gbps PKG

The bonding wire length is minimized (1,800 µm 630 µm), by cutting power/ground rings.

[ Previous Design ] [ Previous Design ] [ Proposed Design ] [ Proposed Design ]

630 µm 630 µm 1,8 0 0 µm 1,8 0 0 µm

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High P/G Plane Impedance made by P/G Plane Resonance High P/G Plane Impedance made by P/G Plane Resonance

(1,0)/(0,1) : 518MHz (1,1) : 743MHz

Low Impedance

0.02 0.04 0.06 0.08 0 1 0.05 0.1 0.02 0.04 0.06 0.08 0 1 0.05 0.1

Mode Suppression

0.1 0.12 0.14 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.1 0.12 0.14 0.02 0.04 0.06 0.08 0.1 0.12 0.14

P/G Plane

Center Located

(2,0)/(0,2) : 1043MHz (2,2) : 1493MHz

0.02 0.04 0.06 0.1 0.02 0.04 0.06 0.1

( )

2 2

2 1 ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = b n a m f

r mn r

π π ε ε μ π

0.08 0.1 0.12 0.14 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.05 0.06 0.08 0.1 0.12 0.14 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.05

High Impedance

cm b a 14 = =

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Spectrum Analyzer Measurement of P/G Plane Edge Radiation Spectrum Analyzer Measurement of P/G Plane Edge Radiation

500 MHz CLK

10

Bm]

100 TV2 SA Measurement TV2 P/G Plane Impedance 1478

• 10

PPG) [dB

10 100

P/G Pla

• 3rd
• 30

n (SA-P

1

ane Imp

0.1

• 50

Radiatio edance

0.01

(7cm 7cm)

TV2

• 70

Edge R [Ω]

(7cm,7cm) 14cm

Frequency [GHz]

0.5 1 1.5 2 2.5 3

Frequency [GHz]

14cm

Short Via

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q y [ ]

q y [ ]

plane cavity resonance modes

Power/Ground Network Impedance Power/Ground Network Impedance 20l |Z |

(2,0) plane cavity resonance modes

20log|ZPDN|

(1/4,0) (1,0) (1,1) (2,0) Parallel circuit resonance PKG-level PDN (1/4,0)

• 20dB/dec

lines

Chip-level PDN Cde

deca cap2 p2

L

de deca cap2 p2

Cde

deca cap1 p1

ωLTotal_Loop3 ωLTotal_Loop1 ωLTotal_Loop2 Series circuit resonance

20dB/dec

plane cavity resonance modes

20dB/dec lines

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log f

plane cavity resonance modes

Effect of On-chip PDN Design Effect of On-chip PDN Design 20l |Z |

(2,0) plane cavity resonance modes

20log|ZPDN|

(1/4,0) (1,0) (1,1) (2,0) On-chip Inductance (1/4,0) Chip-level PDN On-chip decap On-chip ESR

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log f

On-chip PDN

• Decoupling capacitors using oxide capacitance and MIM

capacitance

• Cost sensitive, die size

ESR id ti d d

• ESR considerations needed
• On-chip inductance dominant > 10GHz
• On-chip PDN resonance > 10GHz

O hi PDN di t di t d li

• On-chip PDN: direct radiated coupling source

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Motivation –Cross-sectional View of E mbedded Film Capacitor Motivation –Cross-sectional View of E mbedded Film Capacitor

1 Removal of SMD Passive Componen GND to Chip VDD to Chip

• 1. Removal of SMD Passive Componen

(Enhanced Routibility)

Embedded Film Capacitor

• 2. Short Via Length

(Low Via Inductance)

• 3. Small Thickness

(Low Inductance) High Dielectric Material

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g (High Capacitance)

Fabricated Test Vehicles (with Thin Film Embedded Capacitor) Fabricated Test Vehicles (with Thin Film Embedded Capacitor)

A

Vehicle Code Dielectric Thickness Dielectric Constant (DK)

50 μm 4.6

Capacitance/cm2

81.46 pF

Total Capacitance (5cm x 5cm with 2 pairs)

4.07 nF B C 25 μm 12 μm 4.6 4.6 162.91 pF 339.40 pF 8.15 nF 16.97 nF D E 10 μm 10 μm 16 25 1416.64 pF 2213.50 pF 70.83 nF 110.68 nF 25μm 50μm 12μm “A” with x50 “A” with x100 “A” with x500 “B” with x500 “C” with x500

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Measured Impedance Curves (Discrete, Low DK “C” , High DK “E”) Measured Impedance Curves (Discrete, Low DK “C” , High DK “E”)

20 30

B ohm]

With Thin Film Embedded Capacitor 16 x 100nF Discrete Capacitors TM02/20 Mode Resonance (5cm x 5cm)

10

dance [dB

(Thickness : 12μm, DK : 4.6) – “C” With Thin Film Embedded Capacitor (Thickness : 10μm, DK : 25) – “E”

• 20
• 10
• und Impe

Significant Improvement over GHz With Thin Film Embedded Capacitor

• 40
• 30

Power/Gro

Improvement at low frequency range with High DK Embedded Material

• 50

1 10 100 1000 3000

Frequency [MHz] P

with High-DK Embedded Material

Significant improvement over GHz with Thin Film Embedded Capacitor (Very low ESL of Embedded Capacitor) More improvement at low frequency range with high-DK embedded capacitor (More Capacitance)

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Measured SSN (No De-Cap. Vs. Discrete De-Cap.) Measured SSN (No De-Cap. Vs. Discrete De-Cap.)

3.5

SSN [V]

Vp-p : 370.2 mV

No Decoupling Capacitor

3.1 3.3

Measured S

4 8 12 16 20

Time [nsec] M ]

3 3 3.5

ed SSN [V]

Vp-p : 123.8 mV

16 x 100nF Discrete Capacitors High-frequency harmonic was amplified with discrete capacitors

3.1 3.3

Measure

4 8 12 16 20

Time [nsec]

High frequency harmonic was amplified with discrete decoupling capacitors (as expected with impedance curve)

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Measured SSN (Discrete, Low DK “C” , High DK “E”) Measured SSN (Discrete, Low DK “C” , High DK “E”)

3.5

SSN [V]

With Thin Film Embedded Capacitor (Thickness : 12μm, DK : 4.6) – “C” Low-Frequency Harmonic was appeared with Low DK Embedded Capacitor

3.1 3.3

Measured S

Vp-p : 49.4 mV 4 8 12 16 20

Time [nsec] M ]

3 3 3.5

ed SSN [V]

With Thin Film Embedded Capacitor (Thickness : 10μm, DK : 25) – “E”

3.1 3.3

Measure

Vp-p : 10.6 mV SSN was almost suppressed with High-DK thin film embedded capacitor 4 8 12 16 20

Time [nsec]

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PDN Design Methods

• Frequency dependent capacitance and inductance control
• Increase of decoupling Capacitance depending frequency range
• Increase of decoupling Capacitance depending frequency range

(on-chip, on-package, on-PCB, lumped, embedded)

• Decrease of Inductance (line, plane, via, wire, bonds, decoupling

capacitors )

• Control resonances (lumped, planar cavity, on-chip, inter-level):

avoid overlap with clock and harmonic frequencies

• Control ESR to reduce peak resonance impedance
• Evaluate dc ESR for dc voltage drop estimation

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Proposed Modeling Method for Chip-Package-PCB Hierarchical PDN Proposed Modeling Method for Chip-Package-PCB Hierarchical PDN

x f y f Bond-wire

4 1

Chip-level PDN

1 8

Chip-level PDN Package le el PDN

2

P k l l Bond-wire

4 1

Fringing Field

9

Fringing Field

8

Package-level PDN Ball Inter-level Coupling

7 5 2

Package-level PDN

2

Fringing

9 9

PCB-level PDN Via

3

Vi

6

Inter-level

7

Coupling Ball

5

Field Ground Power S t ti PCB-level Via

6

Coupling

Considering all parts in hierarchical PDN and merging them into one using

Ground Segmentation Method PDN

3

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segmentation method

Analysis of Impedance of Test Vehicle at Package Side Analysis of Impedance of Test Vehicle at Package Side

PCB Mode (1 0)&(0 1) PKG Mode (1 0)&(0 1) PKG Mode (2 1)&(1 2)

100

(1,0)&(0,1) PCB Mode (2,0)&(0,2) PCB Mode (2,1)&(1,2) (1,0)&(0,1) PKG Mode (1,1)&(1,1) PKG Mode (2,1)&(1,2)

Adjacent PKG&Chip Effect

100

hm)

C k CPkg+CInt+CChip

PKG Mode (2,0)&(0,2)

10

edance (oh

CPkg+CInt CPkg CPCB+CPkg+CInt+CChip LPkg+Via

1

Impe

LChip+Bondwire LPkg+Via+LInt//Ball LPCB+Via+LPkg+Via+LInt//Ball

0.1

LPCB+Via LPkg+Via LInt//Ball

Frequency (GHz)

0.1 1 10 20

A quite complicated impedance characteristic composed of chip-package-PCB

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qu te co p cated peda ce c a acte st c co posed o c p pac age C hierarchical PDN is fully analyzed.

Verification of Proposed Modeling Method (Corner on Chip) Verification of Proposed Modeling Method (Corner on Chip)

1000 100 1000 Measurement Proposed Model

Chip (1,0)&(0,1)

Chip

ce (ohm)

100 10 CPkg+CInt+CChip CPkg+CChip LPkg+Via+Bondwire+LChip LChip CChip Package

Impedanc

10 1 LPCB+Via+LPkg+Via+Bondwire+LInt//Ball+LChip LPkg+Via+Bondwire+LInt//Ball+LChip C C C C PCB 1 CPCB+CPkg+CInt+CChip 0.1 0.1 1 10 20

Frequency (GHz)

The impedances at corner probe pad on chip Frequency : 100MHz to 20GHz 5 high impedance peaks 4 peaks interactions

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p 1 peak mode resonance of chip

Need for Estimation of High Impedance Peak in Hierarchical PDN Need for Estimation of High Impedance Peak in Hierarchical PDN

Hi h i d i hi hi l PDN f i i bl f f d d i EMI Power/Ground Noise High impedances in hierarchical PDN from interactions generate problems of system performance degradation.

current nce

VSSN=ZPDN × ICircuit

Impedan

Signal Degradation

RF /Analog

RF Sensitivity

Frequency

Digital RF /Analog Terahertz Interconnection and Package Laboratory

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34 A precise simulation and analysis of hierarchical PDN is needed.

PDN Noise Coupling Paths in chip and package

• Adjacent interconnections: line, pin, wire
• Via and planes

p

• Conductive substrates
• Common power line, plane
• Common decoupling capacitors

Common decoupling capacitors

• Common return current paths
• Isolation techniques needed: Cost, size increase

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Frequency Spectrum of Digital Clock Waveforms Frequency Spectrum of Digital Clock Waveforms

f(x) f(x)

Time Time

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Waveform and Spectrum of Clock Signal Waveform and Spectrum of Clock Signal

100 150 20

100MHz 200MHz

Fundamental : 100MHz Odd harmonics Even harmonics Fundamental : 200MHz

50

tude (mV)

10ns

• 20

er [dBm]

5ns

• 100
• 50

Magni

• 60
• 40

Powe

5 10 15 20

• 200
• 150

Time (ns)

500 1000 1500 2000 2500 3000

• 80

Frequency [MHz]

100MHz 200MHz

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Spectrum of Wireless Mobile Communication Systems Spectrum of Wireless Mobile Communication Systems

S-DMB T-DMB GPS WI-FI Bluetooth TPMS AM FM WiBro

UWB UWB

TPMS RF-ID

주파수

174~216MHz 2.6GHz 1227.60MHz 1575.42MHz 2.3GHz 3.1~4.8GHz 7.2~10.2GHz 535~1,705kHz 2.4GHz 433.92MHz 88~108MHz 900MHz 88 108MHz

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Setup for Analysis Setup for Analysis

Pulse Pattern Generator (PPG) LO Signal Observation Factors : 1. Transfer Impedance ( 1 , 2 ) 2. Noise Coupling Ratio ( 1 , 3 ) 3 Output Waveform ( 3 )

• LO Frequency : 915.5MHz
• LO Voltage : 400mV Pulse

LO Signal 3. Output Waveform ( 3 ) Output Signal Port2 Port3

• Frequency : 500kHz
• Power : -2dBm
• Voltage : 250mV
• Voltage Gain : 12dB

p g Port1 Combine Signal Generator (SG) Balun DC 2.5V

• Frequency : 915MHz

14

RF Signal r

• Frequency : 40kHz , 150MHz, 900MHz
• Voltage : 80mV Pulse

P/G Noise Balun

• Power : -14dBm
• Voltage : 60mV Sine Wave

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Basic Performance of Designed Mixer Basic Performance of Designed Mixer

VDD Double Balanced Mixer Out+ Out- TSMC 0.25um Process Target Frequency : 860 ~ 960 MHz LO + LO + Gain : 10 ~ 12 dB P1dB : - 5dBm RF I solation : -30dB LO - RF+ RF I solation : -30dB LO I solation : -25dB Direct Conversion Frequency : 500kHz bias RF- 500kHz

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On-chip Decap. E ffect : Transfer Impedance ( Simulation ) On-chip Decap. E ffect : Transfer Impedance ( Simulation )

900MHz 900MHz (1,0) (1,1) (λ/4)

Without On-Chip Decap. VS With On-Chip Decap.

20 30 dB ) 900MHz 900MHz (0,1) ( , ) 10 20 pedance ( d Wirebond+ On-chip Decap. Capacitance

• 20
• 10

ansfer Imp On-chip Decap Effect (112pF).

• 40
• 30

Without On-chip decap. With On-chip decap.

Tra 10M 100M 1G Frequency ( Hz )

• When on-chip decoupling capacitor is designed , transfer impedance decreases more than the

case without on-chip decoupling capacitor over 600MHz

• > Transfer impedance decreases when design on-chip decoupling capacitor in 900MHz.

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41 s e ped ce dec e ses w e des g

• c

p decoup g c p c o 900 .

On-chip Decap. E ffect : Output Spectrum (Measurement) On-chip Decap. E ffect : Output Spectrum (Measurement)

Spectrum Spectrum ( Scaled Up ) 13 5B

( 900MHz, -51dBm)

Bm ) Bm )

• 20
• 40

Without Decap. With Decap. Without Decap. With Decap.

13.5B

( 900MHz, -64.5dBm)

Power ( dB Power ( dB

60

• 40
• 60

Frequency ( MHz ) P Frequency ( GHz ) P

0.5 1 1.5 2

• 80
• 60
• 80
• 100

890 895 900 905 910

• Switching noise of output waveform with on-chip decoupling capacitor decreases in 13.5dB a

frequency of 900MHz compared to the case without on-chip decoupling capacitor . frequency of 900MHz compared to the case without on chip decoupling capacitor .

• > Verified effect of design on-chip decoupling capacitor in RF or LO frequency band.

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Off-chip Decap. E ffect : Transfer Impedance (Simulation) Off-chip Decap. E ffect : Transfer Impedance (Simulation)

150MHz

Without Off-Chip Decap. VS With Off-Chip Decap.

dB ) 20 30

Off-chip Decap. Off-Chip Capacitor : L1= 540pH C1=101nF R1 =17mΩ

pedance ( d 10 20

p p Effect L1= 540pH , C1=101nF , R1 =17mΩ

ansfer Imp

• 10

Capacitance I nductance Tra

• 30
• 20

Without Off-chip decap. With Off-chip decap.

10k 100k 1M 10M 100M 1G Frequency ( Hz )

• When additional off-chip decoupling capacitor is designed , transfer impedance decreases

more than the case without additional off-chip decoupling capacitor from 2MHz to 200MHz

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• > Transfer impedance decreases when design on-chip decoupling capacitor in 150MHz.

Off-chip Decap. E ffect : Output Spectrum ( Measurement ) Off-chip Decap. E ffect : Output Spectrum ( Measurement )

Spectrum Spectrum ( Scaled Up )

• 50
• 40

Without Decap. With Decap.

( 150MHz, -44.5dBm)

( 150MHz, -44.5dBm)

p p ( p ) Bm ) m )

• 50
• 40

12.2dB

• 50
• 40

Without Decap. With Decap. Without Decap. With Decap.

70

• 60

( 150MHz, -56.7dBm)

Power ( dB

• wer ( dBm
• 60
• 70

( 150MHz, -56.7dBm)

• 60
• 70

100M 200M 300M 400M 500M

• 80
• 70

Frequency ( MHz ) P Frequency ( MHz ) Po

100 200 300 400 500

120 140 160 180 200

• 80

100

• 80

q y ( ) eque cy ( )

• Switching noise of output waveform with off-chip decoupling capacitor decreases in 12.2dB a

frequency of 150MHz compared to the case without off-chip decoupling capacitor . frequency of 150MHz compared to the case without off chip decoupling capacitor .

• > Verified effect of design off-chip decoupling capacitor in IF frequency band.

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Problem by Power and Ground Noise Problem by Power and Ground Noise

Digital RF & Analog

DAC

PA LNA PLL BPF LNA LNA LNA

ADC

Key circuit Key circuit Unwanted DC Offset System Failure!!

OPamp

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DC Output Offset with Proposed and Conventional Analysis DC Output Offset with Proposed and Conventional Analysis

P Digital OP amp P

DC Output Offset with Conventional Analysis

Digital P OP amp P

DC Output Offset with Proposed Analysis

100mV 100mV 100mV

60

_ + G G G Bonding Wire _ + G Package PDN Chip PDN

50

t (mV)

Conventional analysis Proposed analysis

30 40

utput Offse

10 20

DC O

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Frequency (GHz)

C id bl Di i i b DC O Off

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Considerable Distinction between DC Output Offset with and without Consideration of PDN

SSN Sensitive Circuits in IC

• VCO: Voltage Controlled Oscillator
• LNA: Low Noise Amplifier

PLL Ph L k d L

• PLL: Phase Locked Loop
• ADC: Analog to Digital Converter
• DAC: Digital to Analog Converter

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SSN Isolation Methods

• Decoupling

Decoupling

• Filtering
• Slot
• Split

Split

• Shielding
• EBG strictures
• Separated power supply/decoupling/return current path

Separated power supply/decoupling/return current path

• Separated interconnections: lines, pins, pads, vias
• Separated planes, layers
• Increased separation distance

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• Increased separation distance

PDN Noise Isolation Methods PDN Noise Isolation Methods

Chip

Digital PDN Analog/RF PDN

PCB Package Ch A B

Chip Level Package/PCB Level

A B

p

• Split On-chip Metal PDN Bus
• Guard Ring (P+/ N+/ Deep-Nwell type)
• On-chip Decoupling Capacitor

Internal Voltage Regulator g

• Split Power/Ground Planes
• On-Package/PCB Decoupling Capacitor

(Discrete type, Embedded type) Electromagnetic Band Gap (EBG)

• Internal Voltage Regulator
• Electromagnetic Band Gap (EBG)

Frequency dependency of noise isolation Z21 l i i th f d i

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Z21 analysis in the frequency domain

The isolation methods of each hierarchical PDN The isolation methods of each hierarchical PDN

e [Ω]

104

Split PCB PDN/Split Package PDN Merged PCB PDN/Merged Package PDN Split PCB PDN/Split Package PDN+off chip decap

Impedanc

102

Split PCB PDN/Split Package PDN+off-chip decap. Split PCB PDN/Split Package PDN+off-chip decap.+on-chip decap.

Transfer I

1

By Split

10-2

p .

• n-chip

decap.

1M 10M 100M 1G 3G 10-4

• ff-chip

decap

• d

Frequency [Hz]

• By split of PCB and package level PDN,

the PDN transfer impedance can be suppressed except around 10MHz.

• By adding on-/off-chip decoupling capacitor

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• By adding on-/off-chip decoupling capacitor,

the PDN transfer impedance can be suppressed in both low and high frequency region.

Stack-up for Transceiver SiP [ 7 layer] Stack-up for Transceiver SiP [ 7 layer]

• Thickness = 1.3 mm, Size: 20mmx20mm,
• Ceramic: Dupont (Dielectric Constant = 7.4, Loss Tangent = 0.001)
• Die: 7, Decap: 5 개, Ball: 287, Wire-bonding: 53 개
• 7 Layers

Heat Sink 600 um 500 um Short-wire Signal/Filter Lines Ground Plane Chip Pads

Die

200 um 100 um EBG1 EBG2 Ground Plane 100 100 um 100 um Power Plane BGA 200 um 100 um

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Transceiver without DS-EBG Transceiver without DS-EBG

12 17 dB 12 33 dB

• 12.17 dBm

at 9 GHz

• 12.33 dBm

at 9GHz

• 43 dBm

8 999997 GH at 8.999997 GHz

< Without Power/Ground Noise > < With Power/Ground Noise >

Po er/Gro nd noise generates a 43 dBm of n anted Power/Ground noise generates a -43 dBm of unwanted signal near the output signal.

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Transceiver with DS-EBG Transceiver with DS-EBG

12 17 dB 12 33 dB

• 12.17 dBm

at 9 GHz

• 12.33 dBm

at 9GHz

• 64 dBm

at 8.999997 GHz 21 dB Suppression

< Without Power/Ground Noise > < With Power/Ground Noise >

DS EBG s ccessf ll s ppresses the n anted signal b 21 DS-EBG successfully suppresses the unwanted signal by 21 dB.

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Proposed On-Interposer E BG Structure Proposed On-Interposer E BG Structure

Capacitive P/G mesh

Width: 80um Space: 120um

W

Space: 120um

W S

Inductive P/G mesh Inductive P/G mesh

Width: 40um Space: 360um

W S Terahertz Interconnection and Package Laboratory

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Measurement Results (1/ 2) Measurement Results (1/ 2)

• 10

TV A (Mesh) TV B (EBG)

Mesh PDN

30

• 20

21 (dB) TV B (EBG)

Mesh PDN

• 40
• 30

ficients, S

Stopband

• 60
• 50

ing Coeff

• 80
• 70

Coupl

Interposer EBG

2 4 6 8 10 12 14 16 18 20

• 90

Frequency (GHz)

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Frequency (GHz)

Measurement Results (2/ 2) Measurement Results (2/ 2)

• Switching noise input at port 1 using 500mVpp clock signal

C l d i t b d t t 2

• 10

TV A (M h)

• 10

TV A (M h)

• Coupled noise spectrum probed at port 2
• 30
• 20

um (dBm) TV A (Mesh) TV B (EBG)

• 30
• 20

um (dBm) TV A (Mesh) TV B (EBG)

500MHz 1GHz

• 50
• 40

ed Noise Spectru

• 50
• 40

ed Noise Spectru 2 4 6 8 10 12 14 16 18 20

• 70
• 60

Couple 2 4 6 8 10 12 14 16 18 20

• 70
• 60

Couple 2 4 6 8 10 12 14 16 18 20 Frequency (GHz) 2 4 6 8 10 12 14 16 18 20 Frequency (GHz) Terahertz Interconnection and Package Laboratory

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Proposed 3D Clock Distribution Scheme Proposed 3D Clock Distribution Scheme

3-D Stacked Chip Star-wiring I/O Clock Distribution for Low Jitter, Skew, and Delay

lossless of bonding-wire & pad free from on both on chip and package power supply noise

Clock Distribution Path using Bonding Wire DLL Output Driver DLL Replica Path Star-wiring DLL DLL Chip Stacked Chip I/O Buffer DLL Chip Ball Grid Array Package I/O Buffer

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Enhanced Clock Jitter Performance of the Proposed Scheme Enhanced Clock Jitter Performance of the Proposed Scheme

Conventional On-chip I/O Clock Distribution Scheme 3D Stacked Chip Star-wiring I/O Clock Distribution Scheme

300mV/div] 300mV/div]

500MHz Clock 500MHz Clock

Voltage [3 Voltage [3

• Peak-to-Peak Jitter : 146ps
• Peak-to-Peak Jitter : 34ps

p RMS Jitter : 22ps

Time[100ps/div]

• Peak-to-Peak Jitter : 34ps

RMS Jitter : 5ps

Time[100ps/div] 3D-stacked chip star-wiring clock scheme provides low clock jitter compared with

• n-chip clock scheme (77% jitter reduction)

It is devised to enable the clock signal delivery to be free from on-chip digital

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Advantages of Proposed PCR CDN for 3D Stacked Chip Package Advantages of Proposed PCR CDN for 3D Stacked Chip Package

Clock path

HRM F/F

Wire-bond as an inductive termination

DLL

Clock Data I/O Synchronous digital chip

Quarter- wavelength resonator Jitter is filtered

Data I/O Package sub. LTCC interposer

filtered

Package ball

Package-level implementation One planar cavity resonator (not grid connected) p y ( g )

• Jitter is filtered by high-Q bandpass filter utilizing a package level quarter-wavelength

planar cavity resonator

• Reduction of the number of cascaded repeaters

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• Reduction of the number of cascaded repeaters

Originalities of Proposed PCR CDN for 3D Stacked Chip Package Originalities of Proposed PCR CDN for 3D Stacked Chip Package

Wire-bond Standing wave voltage amplitudes Planar cavity as an inductive termination

(V)

voltage amplitudes Planar cavity I/O buffer I/O buffer Min. Max.

• Uniform phase and uniform amplitude standing wave is used for clock

distribution

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Quarter-wavelength Resonator with Inductive Termination Quarter-wavelength Resonator with Inductive Termination

• pen
• pen
• pen

Inductive termination Voltage Voltage Incident wave λ/2 λ/4 l

• pen

short Voltage Voltage λ/4

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Measure E yd-diagram of PCR CDN with Noise Measure E yd-diagram of PCR CDN with Noise

1 2

Clock source before distribution Distrbuted clock at planar cavity resonator output

1 2 (V) 1.2 Pk-to-pk jitter = 98 ps Pk-to-pk jitter = 28 ps (V) 1.2 Voltage Eye-opening = 920mV Eye-opening = 1720mV Voltage

• 1.2

100 200 400 300 Time (psec) 100 200 400 300 Time (psec)

• 1.2

(p ) (p )

Source clock Distrbuted clock

• Clock frequnecy : 1.55 GHz

Pk-to-pk jitter 98 ps 28 ps Eye-opening 920 mV 1720 mV

• Clock magnitude : 1 Vp-p
• Switching noise : 300 mV

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Unique Research Focus Unique Research Focus

High-performance Mixed Mode System

System on Chip (On Chip Level)

Signal Integrity

(On-Chip Level) System in Package

Signal Integrity

Low Low Noise Noise and and High High-Integration Integration y g (On-Package Level) Co-Design

Electromagnetic I t f P I t it

High High-Integration Integration Desi Design Module, PCB, Cabling (System Level)

Interference Power Integrity

I mprovement of Reliability Performance Design Cycle Cost

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I mprovement of Reliability, Performance, Design Cycle, Cost

Conclusion Conclusion

• Significant noise coupling occurs from digital PDN to noise

sensitive RF and analog circuits on a same SiP.

• The clock frequencies and harmonic frequencies should be

The clock frequencies and harmonic frequencies should be placed away from the RF carrier frequencies.

• Low PDN impedance should be maintained.
• PDN resonance frequencies should be placed away not only from

the clock frequencies, and their harmonic frequencies, but also from RF carrier frequencies. q

• Via and wire are a major noise coupling path from digital PDN to

noise sensitive circuits. Noise coupling reduction methods including using PDN design

• Noise coupling reduction methods including using PDN design,

frequency control, filtering, separation/isolation, decoupling, shielding, and grounding techniques.

• Case studies: LNA, Clock distribution network
• Chip-package co-design can provide optimal and cost-effective

solutions

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solutions.