IC220 Set #7: Controlling the Single Cycle Implementation (Chapter Four) 1 Control Selecting the and controlling the based on the • Outline: 1. Overview 2. Controlling the ALU 3. Controlling multiplexors and register writes 2
Reminder: Instruction Encoding 0x7C0 or 0x7C2 0x09 3 Part 1: Control Overview Example #1: add x9, x21, x3 0x458 3 0 21 9 opcode Rm shamt Rn Rd 11 bits 5 bits 6 bits 5 bits 5 bits Example #2: stur x8, [x10, #240] 0x7c0 240 0 10 8 opcode address op2 Rn Rt 11 bits 9 bits 2 bits 5 bits 5 bits add x9, x21, x3 stur x9, [x10, #240] A. What should the register file do? B. What should the ALU do? C. What should the muxes do? D. What should memory do? 4
Part 1 – Control Overview 5 Recall: ALU Control and Symbol ALU operation Function 0000 AND 0001 OR 0010 Add 0110 Subtract 0111 Pass input b 1100 NOR 6
Part 2: ALU Control Scheme Instruction Desired ALU Instruction Opcode ALU operation op action LDUR Load register 11111000010 STUR Store register 11111000000 Branch if 10110100000 CBZ zero ADD Add 10001011000 SUB Subtract 11001011000 10001010000 AND AND ORR OR 10101010000 Note: book uses 2 bit “ALU Op” to help, but we’ll instead directly compute 4-bit “ALU operation” from opcode 7 Part 3: Main Control • Set the muxes and register write signals – To get data to flow to the right places – To store data in the appropriate places • 7 signals: – ALUSrc – MemtoReg – MemRead – MemWrite – Branch – RegDst – RegWrite • Control based on: 8
Part 3 – Main Control 9 EX: 4-3 to 4-4 Example – Main Control for an ‘add’ 10
Recall: Instruction Encoding What detail did our previous pictures overlook? 11 Adding “GetImmediate” module Get Immed 12
“GetImmediate” functionality • Book’s approach: – “SignExtend” unit takes 32 bit input, produces 64 bits output – Possible – but more than just “sign extend” is going on • Our CircuitVerse implementation – “SignExtend” unit replaced with “GetImmediate” – Still 32 bits input – Output depends on datapath width (16 bits in our CV example) – Controlled by 3 bit “ImmOp” signal ImmOp Grab what bits? Sign extend? Inst. type 001 20-5 No IW-type (movz) 100 25-0 Yes B-type (b) 101 23-5 Yes CB-type (cbz) 111 20-12 Yes D-type (ldur, stur) ALU Operation 0110 SUB 0010 0010 0111 13 Recall: Bigger Constants • Most constants are small – 12-bit immediate is sufficient • For the occasional bigger constant MOVZ: move wide with zeros MOVK: move wide with keep • Both accept 16 bit immediates • And, use with “flexible 2nd operand” (shift) MOVZ X9,255,LSL 16 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 MOVK X9,255,LSL 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 1111 1111 14
Support for MOVZ? • Let’s add MOVZ, but ignore the optional LSL shift • IW-type instruction • Example: MOVZ X9, 255 // X9 = 255 1. What must change? 2. Where will new value come from? 3. How will it get there? 15 LEGv8 Encoding Summary 16
Adding MOVZ (part 1 – dataflow) Get Immed 17 Adding MOVZ (part 2 – control) To complete the MOVZ instruction, modify the control chart below (add a new row and any new signals, if necessary). ALU Operation “ImmOp” 0110 XXX SUB 0010 111 0010 111 101 0111 18
How to modify the datapath? (for homework, etc.!) • To add a new instruction, what needs to happen? • Old instructions must still work! • If you add a mux, draw it properly! – Put all the “inputs” on the left side (and label with 0, 1, etc.) – Put the “output” on the right side – Put control/selector bits on top or bottom (don’t confuse them with the inputs!) 19 Support for unconditional branch (b)? • B-type – B 10000 // go to location PC+10000 5 10000 ten 6 bits 26 bits 20
Adding unconditional branch (part 1 – dataflow) Get Immed 21 EX: 4-6 Adding unconditional branch (part 2 – control) To complete the branch instruction, modify the control chart below (add a new row and any new signals, if necessary). ALU Operation “ImmOp” 0110 XXX SUB 0010 111 0010 111 101 0111 22
Our Simple Control Structure • All of the logic is combinational • We wait for everything to settle down, and the right thing to be done – ALU might not produce “right answer” right away – we use write signals along with clock to determine when to write • Cycle time determined by length of the longest path We are ignoring some details like setup and hold times 23 Performance Get Immed 24
Performance Calculation Instruction Functional Units used by the instruction class Class R-type ldur stur cbz Memory (200ps) Final Cycle Time? ALU and adders (100ps) Register file access – read or write (50ps) 25 Performance – extra picture #1 • Calculate cycle time assuming negligible delays except: Memory (200ps), ALU and adders (100ps), Register file access – read or write (50ps) Get Immed 26
Performance – extra picture #2 • Calculate cycle time assuming negligible delays except: Memory (200ps), ALU and adders (100ps), Register file access – read or write (50ps) Get Immed 27 Performance – extra picture #3 • Calculate cycle time assuming negligible delays except: Memory (200ps), ALU and adders (100ps), Register file access – read or write (50ps) Get Immed 28
Evaluation – Single Cycle Approach • Good: • Bad: 29
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