[PPT] - I I I -Vs: I I I V s: From THz HEMT to CMOS J. A. del Alamo and PowerPoint Presentation

SLIDE 1

I I I -V’s: I I I V s: From THz HEMT to CMOS

J. A. del Alamo and D.-H. Kim1

Microsystems Technology Laboratories, MIT

1presently with Teledyne Scientific

2009 Topical Workshop on Heterostructure Microelectronics

Sponsors: Intel, FCRP-MSD Acknowledgements:

August 25-28, 2009

1

Acknowledgements: Niamh Waldron, Tae-Woo Kim, Donghyun Jin, Ling Xia, Dimitri Antoniadis, Robert Chau MTL, NSL, SEBL

SLIDE 2

Outline

Introduction
Near-THz III-V HEMTs
Logic characteristics of III-V HEMTs
III-V CMOS
Conclusions

2

SLIDE 3

The High Electron Mobility Transistor

3

Mimura, JJAPL 1980

SLIDE 4

Modulation doping

High electron mobility in modulation-doped

AlGaAs/GaAs heterostructures

2 DEG at AlGaAs/GaAs interface

Dingle, APL 1978 Stormer, Solid St

4

Comm 1979

SLIDE 5

HEMT circuits

27-stage ring oscillator

E/D logic

“The switching delay of 17 1 ps is the lowest of all 17.1 ps is the lowest of all the semiconductor logic technologies reported thus f ”

5

Mimura, JJAPL 1981

far.”

SLIDE 6

HEMTs in other material systems

InAlAs/InGaAs on InP AlGaAs/InGaAs PHEMT

K tt EDL 1985 1982 Ketterson, EDL 1985 Kastalsky, APL 1982

Also in AlGaN/GaN, Si/SiGe, AlSb/InAs, etc

6

Also with holes in many heterojunction systems

SLIDE 7

HEMT Electronics: “You’ve come a long way baby!”

u

e co e a o g ay baby

7

SLIDE 8

Near THz HEMTs

fT vs time:

800 800 800 800 800 800 800 800

Kim EDL 2008

600

GHz]

600

GHz]

600

GHz]

600

GHz] I I I -V HBTs I I I -V HEMTs

600

GHz]

600

GHz]

600

GHz]

600

GHz] I I I -V HBTs I I I -V HEMTs

400

equency [G

400

equency [G

400

equency [G

400

equency [G

400

equency [G

400

equency [G

400

equency [G

400

equency [G

200

Cutoff Fre

200

Cutoff Fre

200

Cutoff Fre

200

Cutoff Fre SiGe HBTs

200

Cutoff Fre

200

Cutoff Fre

200

Cutoff Fre

200

Cutoff Fre SiGe HBTs

1985 1990 1995 2000 2005 2010

Year

1985 1990 1995 2000 2005 2010

Year

1985 1990 1995 2000 2005 2010

Year

1985 1990 1995 2000 2005 2010

Year Si CMOS SiGe HBTs

1985 1990 1995 2000 2005 2010

Year

1985 1990 1995 2000 2005 2010

Year

1985 1990 1995 2000 2005 2010

Year

1985 1990 1995 2000 2005 2010

Year Si CMOS SiGe HBTs

8

Year Year Year Year Year Year Year Year

For over 20 years, fT (III-V’s) > fT (Si)

SLIDE 9

Near THz HEMTs

fT vs fmax:

1000

max

f fτ

300 400 500 600 700 = favg =

800 1000

MIT HEMTs III-V HEMTs III-V HBTs

max τ

avg

400 600

ax [ GHz ]

Kim IEDM 2008

200 400

fm

200 400 600 800 1000

fT [ GHz ]

9

III-V HEMT: only device with ft, fmax>600 GHz

SLIDE 10

I I I -Vs for CMOS?

Si scaling running into increasing difficulties:

3

< Historical > < Extrapolated >

3

< Historical > < Extrapolated > The scaled Si CMOS “performance gap”

3

< Historical > < Extrapolated >

3

< Historical > < Extrapolated >

3

< Historical > < Extrapolated >

3

< Historical > < Extrapolated > The scaled Si CMOS “performance gap”

Courtesy of Dimitri Antoniadis (MIT)

x 10

15

n)

G

S D

1 5 2 2.5 Delay (ps)

< Historical > < Extrapolated >

1 5 2 2.5 Delay (ps) 1 5 2 2.5 Delay (ps)

< Historical > < Extrapolated >

1 5 2 2.5 Delay (ps)

< Historical > < Extrapolated >

1 5 2 2.5 Delay (ps) 1 5 2 2.5 Delay (ps)

< Historical > < Extrapolated >

1 5 2 2.5 Delay (ps) 1 5 2 2.5 Delay (ps)

< Historical > < Extrapolated >

1 5 2 2.5 Delay (ps) 1 5 2 2.5 Delay (ps)

< Historical > < Extrapolated >

1 rge (C/micro

“parasitic” charge

“15 nm” target

0.5 1 1.5 Intrinsic

“15 nm” target

0.5 1 1.5 Intrinsic 0.5 1 1.5 Intrinsic

“15 nm” target

0.5 1 1.5 Intrinsic

“15 nm” target

0.5 1 1.5 Intrinsic 0.5 1 1.5 Intrinsic

“15 nm” target

0.5 1 1.5 Intrinsic 0.5 1 1.5 Intrinsic

“15 nm” target

0.5 1 1.5 Intrinsic 0.5 1 1.5 Intrinsic

0.5 Gate Cha

channel charge

15 nm target

20 40 60 80 100 120 CMOS Generation (nm)

15 nm target

20 40 60 80 100 120 CMOS Generation (nm) 20 40 60 80 100 120 CMOS Generation (nm)

15 nm target

20 40 60 80 100 120 CMOS Generation (nm)

15 nm target

20 40 60 80 100 120 CMOS Generation (nm) 20 40 60 80 100 120 CMOS Generation (nm)

15 nm target

20 40 60 80 100 120 CMOS Generation (nm) 20 40 60 80 100 120 CMOS Generation (nm)

15 nm target

20 40 60 80 100 120 CMOS Generation (nm) 20 40 60 80 100 120 CMOS Generation (nm)

20 40 60 80 100 120 CMOS Generation (nm)

10

Parasitics becoming overwhelming need higher current

SLIDE 11

Transistor as switch

In logic applications transistor operates as switch

Interested in:

ON current (ION)
OFF current (IOFF)

( OFF)

VT
VT dependence on Lg
VT dependence on VDS (DIBL)
Subthreshold swing (S)
Device footprint
Gate capacitance

11 11

Operating voltage (VDD)

SLIDE 12

How Do I I I -V FETs Look for Logic?

Logic Characteristics of InGaAs High-Electron Mobility Transistor

Kim, IEDM 2006

Lg ~ 60 nm

Source Drain

source drain gate

Substrate is InP

Source

InP InGaAs cap InAlAs insulator

Substrate is InP
Channel is In0.7Ga0.3As

μ > 10 000 cm2/V s at 300K

12 12 InGaAs channel InAlAs buffer

μ > 10,000 cm /V.s at 300K

Barrier is In0.52Al0.48As

SLIDE 13

60 nm I nGaAs HEMT

10

4

10

3

ID IG VDS = 0.5 V 0.5 VGS = 0.5 V 10

6

10

5

10 VDS = 0.05 V

ID

A/μm]

G

Id

0.3 0.4 VGS = 0.4 V

GS

mm]

10

9

10

8

10

7

VDS = 0.5 V

ID & IG [A

IG

Ig

0.1 0.2 VGS = 0.2 V VGS = 0.3 V

ID [A/m

1.00
0.75
0.50
0.25

0.00 0.25 0.50 10

10

10

9

VGS [V]

0.0 0.2 0.4 0.6 0.8 0.0 VGS = 0.1 V

VDS [V]

At 0.5 V:

Kim, IEDM 2006

13 13

VT= -0.02 V, S= 88 mV/dec, DIBL= 93 mV/V, Ion/Ioff > 104

SLIDE 14

Benchmarking Against Si MOSFET: Gate Delay (CV/ I ) vs L Gate Delay (CV/ I ) vs. Lg

10

For V at 1 μA/μm

psec]

For VT at 1 μA/μm Kim IEDM 2006

1 In0.7Ga0.3As HEMTs (VDD = 0.5V)

E DELAY [p

Si data from Chau, T-Nano 2005 Kim, IEDM 2006

GATE

Si NMOSFETs (VDD = 1.1~1.3V) 10 10

1

10

2

10

3

0.1

Gate Length, Lg [nm]

14 14

Gate delay comparable to Si, in spite of lower voltage

SLIDE 15

Benchmarking Against Si MOSFET: S & DI BL vs L S & DI BL vs. Lg

Kim, IEDM 2006

180

]

180

Si FETs (IEDM)

InGaAs HEMTs ]

400 400

Si FETs (IEDM)

InGaAs HEMTs

120 140 160

pe [mV/dec]

120 140 160

pe [mV/dec]

200 300

mV/V]

200 300

mV/V]

80 100 120

threshold Slo

80 100 120

threshold Slo

100 200

DIBL [m

100 200

DIBL [m

10 100 60 80

Gate Length [nm] Sub

10 100 60 80

Gate Length [nm] Sub

10 100

Gate Length [nm]

10 100

Gate Length [nm]

At Lg=60 nm, InGaAs HEMT as good as Si MOSFET C thi d i t l t th 15 d ?

15 15

Can this device concept scale to the 15 nm node? How will its performance compare with Si?

SLIDE 16

HEMT scaling

Key dimensions: Lg, tins, tch, Lside
Scaling trajectory:

– Lg ↓ Lg ↓

tins ↓
tch ↓
Lside?

16 16

SLIDE 17

I mpact of gate length

VDS=0.5 V

6

x 10

4

VDS = 0.5 V

4

IOFF

2

ION/

tch = 13 nm tins = 10 nm L id = 150 nm

100 200 300 400 500

Lg [nm]

Lside 150 nm

Lg↓

– Ion/Ioff drops in the sub-200 nm regime

17

n
ff

p g – SCE worsen

17

Kim, IEDM 2006

SLIDE 18

I mpact of barrier thickness

VDS=0.5 V

6

x 10

4

tch = 13 nm L 150

4

OFF

Lside = 150 nm

2 tins = 10 nm tins = 6.5 nm

ION/I

100 200 300 400 500 tins = 3 nm

Lg [nm]

tins↓

– Ion/Ioff worsens for long Lg due to IG↑ and Rs↑

18

n
ff

g

g G↑ s↑

– SCE and scalability improve

18

Kim, IEDM 2006

SLIDE 19

I mpact of side recess length

200 Lside = 50 nm Lside = 150 nm L = 350 nm

VDS=0.5 V

10

5

150 Lside = 350 nm

mV/dec]

tch = 13 nm

10

4

ON/IOFF

100

S [m

ch

tins = 10 nm

10

3

Lside = 50 nm Lside = 150 nm Lside = 350 nm

IO

L

100 200 300 400 50

Lg [nm]

100 200 300 400 10

2

side

LG [nm]

Lside↑

– Ion/Ioff scalability improves B tt SCE

Kim, ISDRS 2007

19

– Better SCE – But… minimum Lside shortens as tins↓ tch↓

19

SLIDE 20

I mpact of channel thickness

tch↓ performance degradation

increase InAs composition in channel

100

dec]

tins = 3-4 nm Lside = 150 nm

10

5

InAs HEMTs tch = 10 nm

80 90

swing [mV/d

In0.7Ga0.3As HEMTs 10

μn = 13,000 cm

2/V-s ON/IOFF

70 InAs HEMTs

ubthreshold

VDS=0.5 V

VDS = 0.5 V IO In0.7Ga0.3As HEMTs tch = 13 nm

μn = 10,000 cm

2/V-s

10 100 60

S Lg [nm]

100 10

4

DS

LG [nm]

20 20

tch↓ + x(InAs)↑

Ion/Ioff↑, better scalability, better SCE

Kim, IEDM 2007

SLIDE 21

Scaled HEMTs: Benchmarking with Si

160 180

ec.]

Si FETs (IEDM) Triple recess: IEDM 07 Pt sinking

160 180

ec.]

Si FETs (IEDM) Triple recess: IEDM 07 Pt sinking

160 180

ec.]

Si FETs (IEDM)* Pt sinking: IEDM 08

160 180

ec.]

Si FETs (IEDM)* Pt sinking: IEDM 08 10

c]

iedm06

120 140

d swing [mV/de

120 140

d swing [mV/de

120 140

d swing [mV/de

120 140

d swing [mV/de

1

iedm07 DELAY [psec

80 100

Subthreshold

80 100

Subthreshold

80 100

Subthreshold

80 100

Subthreshold iedm06 iedm07 iedm08

InAs HEMTs (VCC = 0.5V)

GATE D

Si NMOSFETs (VCC = 1.1~1.3V)

iedm08

VDD=0.5 V

10 100 60

Gate Length [nm]

10 100 60

Gate Length [nm]

10 100 60

Gate Length [nm]

10 100 60

Gate Length [nm] iedm08

10 10

1

10

2

0.1

Gate Length, Lg [nm]

Scaled to Lg=30 nm
Superior short-channel effects as compared to Si

MOSFETs MOSFETs

Lower gate delay than Si MOSFETs at lower VDD

21

SLIDE 22

What’s behind such performance?

3E+7 4E+7

VDS=0.5 V

2E+7 3E+7

nj (cm/s)

In0.7Ga0.3As channel t 13

ITRS

0E 0 1E+7

vi

tch = 13 nm tins = 4 nm Lside = 150 nm

Strained Si

0E+0 50 100 150

Lg (nm)

High electron velocity in channel (vinj>3x107 cm/s)
Medium-K barrier
Quantized channel
2DEG extrinsic region

22

utstanding SCE

SLIDE 23

30 nm I nAs HEMT

0 8

40 H

Lg = 30 nm tch = 10 nm

0.6 0.8

0.3 V VGS = 0.4 V

30 U H21

tins = 4 nm Lside = 80 nm

0.4

ID [A/mm]

10 20 fT = 628 GHz MAG

Gain [dB]

0.0 0.2 0.4 0.6 0.8 0.0 0.2

10

9

10

11

10

12

10 VGS = 0.1 V VDS = 0.6 V fmax = 331 GHz

Paying attention to SCE pays off in frequency response

VDS [V]

10 10 10 10

Frequency [Hz] 23

fT=628 GHz: highest fT reported on any FET on any

material system

23

Kim, EDL 2008

SLIDE 24

30 nm I nAs HEMT by Pt Sinking by t S g

Lg = 30 nm tch = 10 nm

Kim, IEDM 2008

0.8

50

ch

tins = 4 nm Lside = 150 nm

0.6

VGS = 0.4 V

m]

VGS = 0.5 V

30 40

[dB]

H21

0 2 0.4

GS

ID [mA/μm

20 30

H21, Ug, MAG

Ug MAG

fT=601 GHz fmax=609 GHz

0.0 0.2 0.4 0.6 0.8 0.0 0.2

10

9

10

11

10

12

10

H

VDS = 0.5 V, VGS = 0.3 V

180 nm gate stem height to reduce parasitic capacitance

VDS [V]

10 10 10 10

Frequency [GHz]

24

Enhancement mode FET: VT = 0.08 V
First transistor with both fT and fmax > 600 GHz

24

SLIDE 25

I I I -V HEMT vs. Si CMOS

Intel’s 65 nm CMOS 60 nm HEMT

http://www chipworks com/uploadedImages/Int http://www.chipworks.com/uploadedImages/Int el_PMOS.bmp

Some issues:

Gate shape
Big! [footprint 1000x too big]

25

Non self-aligned contacts

SLIDE 26

Self-Aligned I nGaAs HEMT

V V 0.4 0.5 0.6

/μm)

Vgs – VT = 0.55 V 0 35 V

Waldron, IEDM 2007 Lg=90 nm

0.1 0.2 0.3

Id (mA

0.35 V 0.15 V

SiO W

Air spacer

0.2 0.4 0.6 0.8 1

Vds (V)

1.E-02 Vds = 0.05 V, 0.5 V 90 nm 60 nm

Id

1.E-08 1.E-06 1.E-04

Ig (A/μm)

Ig

VT=60 mV

Self-aligned W non-alloyed ohmic t t

1.E-12 1.E-10

0.6
0.4
0.2

0.2 0.4

Id, I

26

contacts

Vgs (V)

DIBL=55 mV/V, SS=70 mV/dec, Ion/Ioff=8x104, RS=0.24 Ω.mm

SLIDE 27

Contact scaling

Pad c

R

W

R

contact length

W

R

cap c

R

side

R Barrier

R a ie

(54% of RS) To achieve target, need to eliminate barrier under contact high-K gate dielectric required

27

SLIDE 28

High-K gate dielectric also required for tins scaling equ ed o tins sca g

10

4

10

3

tins = 10 nm tins = 7 nm

Lg = 30 nm

10

6

10

5

10

m]

tins = 4 nm

Lg 30 nm tch = 10 nm Lside = 150 nm

ID

10

8

10

7

10

ID, IG [A/μm

IG

10

10

10

9

10 VDS = 0.5 V

t ↓ I ↑

1.00
0.75
0.50
0.25

0.00 0.25 0.50 10

VGS [V]

28

tins ↓ IG↑ Further scaling requires high-K gate dielectric

28

SLIDE 29

From THz HEMT to I I I -V CMOS

Future III-V CMOS Modern III-V HEMT

29 29

SLIDE 30

The High-K/ I I I -V System by ALD

Ex-situ ALD produces high-quality interface:

– Surface inversion demonstrated on p-type InGaAs p yp – Dit in mid ~1011 cm-2.eV-1 demonstrated

Al2O3/In0.52Ga0.47As

f=100 Hz-1 MHz 30 30

Lin, SISC 2008

SLIDE 31

Al2O3/ I n0.75Ga0.25As MOSFETs

10

1

10

2

10

3

Vds=0.8V m)

10

1

10

Id (μA / μm Vds=0.05V

400

Vgs=0.8V

L =160nm 0 8 0 4 0 0 0 4 0 8 10

4

10

3

10

2

Lg= 160 nm

300

0.6V

A/μm)

Lg=160nm

0.8
0.4

0.0 0.4 0.8

Vgs (V) For Vdd= 0.8 V: VT= 0.2V

100 200

0.2V 0.4V

Ids (μA

T

I d(ON)= 399 µA/ µm Gmpk= 633 µS/ µm I on/ I off= 1.6x103 SS 141 mV/ dec

0.0 0.2 0.4 0.6 0.8

0V

Vds (V)

SS= 141 mV/ dec DIBL= 116 mV/ V

Wu, EDL 2009 31

SLIDE 32

The Al2O3/ I nGaAs I nterface

Density-Functional Theory Molecular Dynamics (DFT-MD) simulations show high quality Al2O3/InGaAs interface Ef CB VB Low InGaAs lattice

No midgap states
Fermi level midgap consistent

Low InGaAs lattice distortion with low interface dipole

Chagarov, Surf. Sci., in press

32

SLIDE 33

ALD “Clean-up” Effect

a+3

Ga‐O/S

Ga‐As As2p Ga2p As‐Ga

s‐S A s ‐ A s s+3 a+3

Ga‐O/S

Ga‐As As2p Ga2p As‐Ga

s‐S A s ‐ A s s+3

ALD half-cycle study

ect

Al2O3/In0.2Ga0.8As Sample treated in (NH ) S

Ga

After (NH4)2S etch

As As Ga

After (NH4)2S etch

As As

Sample treated in (NH4)2S
Precursors: TMA + H2O
In-situ XPS analysis

After TMA pulse 1 After TMA pulse 1

In situ XPS analysis

After H2O pulse 1 Aft TMA l 2 After H2O pulse 1 Aft TMA l 2

experiment evolution

After TMA pulse 2 After H O pulse 2 After TMA pulse 2 After H O pulse 2

Clean-up of all As oxides

and reduction of Ga+3 oxides

After H2O pulse 2 After 1nm Al2O3 After H2O pulse 2 After 1nm Al2O3

and reduction of Ga

xides

after first TMA pulse

As-As bonding persistent

1122 1120 1118 1116 1114 e

2O3

Binding Energy (eV) 1329 1326 1323 1320 1122 1120 1118 1116 1114 e

2O3

Binding Energy (eV) 1329 1326 1323 1320

Milojevic, APL 2008

33

SLIDE 34

I I I -V MOSFET architecture 1: I mplanted Self-Aligned MOSFET

2

10

3

Direct deposition of HfO 2 Vd=1V Lg=95nm S.S.=164mV/dec

p a ted Se g ed OS

10 10

1

10

2

Vd=50mV

mA/mm)

DIBL=105mV/V

350 400

Direct deposition of HfO2 V =0~2V in 0 5V step

10

2

10

1

10

Id (m

150 200 250 300

d (mA/mm)

Vg=0 2V in 0.5V step Lg=95nm

0.5

0.0 0.5 1.0 1.5 2.0

V g (V)

0.0 0.5 1.0 1.5 2.0 50 100

Id Vd (V)

10 nm HfO2 by MOCVD
Si I/I + RTA 600 C, 60 s

34

Lg=95 nm

34

Lin, IEDM 2008

SLIDE 35

I I I -V MOSFET architecture 2: MOSFET with regrown ohmic contacts OS t eg o

c co tacts

G In-situ Doped S/D for RS Reduction 500 Step = 0.5 V

μm)

VG-VT = 0 to 3 V 10

3

μm)

V = 1 2 V G In0.4Ga0.6As Reduction

x y

300 400 p

rent ID (μA/μ

LG = 250 nm 10

6

10

5

10

4

urrent ID (A/μ

VDS 1.2 V VDS = 0.1 V In0.53Ga0.47As InP

y

Channel Strain Engineering for Mobility Enhancement 100 200

Drain Curr

10

8

10

7

10

6

Drain Cu

LG = 250 nm

15 nm HfAlO by MOCVD

0.0 0.5 1.0 1.5 2.0

Drain Voltage VD (V)

1

1 2 3

Gate Voltage VG (V)

y

TaN gate, SiON spacers
In-situ Si doped InGaAs S/D by MOCVD (635 C, 2 min)

35

Lg=250 nm

35

Chin, EDL 2009

SLIDE 36

I I I -V MOSFET architecture 3: I mplant-free gate-last MOSFET p a t ee gate ast OS

10 nm GGO by MBE
5 nm AlGaAs/GaAs barrier
5 nm AlGaAs/GaAs barrier
10 nm In0.3Ga0.7As channel
Pt/Au gate

36

g

Lg=180 nm

Hill, EL 2007

VDS=1.5 V

SLIDE 37

Worries…

Can we make 15 nm-class III-V MOSFETs with higher

performance than equivalent Si devices? Wh t i t d b t th t d i ?

What are we going to do about the p-type devices?
Will III-V MOSFETs be reliable?
Will III-V MOSFETs be reliable?
Will III-V CMOS be ready on time?

y

37 37

SLIDE 38

Conclusions

III-Vs attractive for CMOS
III-V CMOS will strongly leverage Si

rather than “beyond Silicon” a III V channel will be an add on to Si rather than beyond Silicon , a III-V channel will be an add-on to Si technology (as Cu, strain and high-K dielectrics have been in the past)

Great challenges ahead:

– Growth of III-V heterostructures on Si with thin buffer layers – Stable and reliable high-K/III-V interface with high interfacial quality g g q y – Nanometer-scale, self-aligned, E-mode FET architecture – High quality p-channel device

38