http://www.megaprocessor.com/ 1 Navigation Check Simple (RISC) - - PowerPoint PPT Presentation

CSE140 - Processors Edited file from Bryan Chin

1

http://www.megaprocessor.com/ 8-bit adder

Navigation Check

• Simple (RISC) Processor

2

Simplified Digital Computer

3

Instruction Store Memory Execute Register File Control

ALU Multiply/Divide

Simplified Digital Computer

4

Instruction Store Memory Execute Register File Control

ALU Add, logic, shift Multiply/Divide

Instruction Types

• Load
• Store
• Control Flow
• Execute

PC

SRAM (single port)

• 32 rows, 32 columns
• Can read or write one row at a time

(32 bits wide)

• Decoder – takes in 5 bits, generates

1 of 32 (one-hot output)

5

Sense Amp Write Driver

WL B+ B-

Memory Cells Memory Cells Memory Cells Memory Cells

32 columns 32 rows

Decoder

Addr[4:0] WE* Data[31:0] Processor Register file MIPS I - 32 registers, 32 bits Need to read 2 operands and write 1 3 ports

Register File – smallish SRAM with more ports

• Processor Register file
• MIPS I - 32 registers, 32 bits
• Need to read 2 operands and write 1
• 3 ports
• Modern processor register files may have

lots of ports (e.g 14 R and 7 W)

6

Sense Amp Write Driver

Make an array of these

WL B+ B-

Memory Cells Memory Cells Memory Cells Memory Cells

32 columns

32 rows

Decoder

WAddr[4:0] WE*

writeData[31:0]

Sense Amp

rdA[31:0] rdB[31:0]

Decoder Decoder

AddrA[4] AddrB[4]

Row Decoder

• 5->32 decoder choses which row
• One decoder per port

7 Addr[0] Addr[1] Addr[2] Addr[3] Addr[4]

A register file is 128 bits wide and contains a total of 1 KB of storage. How many address bits will be required by the row decoder?

• A. 10 bits
• B. 9 bits
• C. 64 bits
• D. 6 bits
• E. None of the above

8

* - B means byte, b means bit

9

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

MUX

1

MUX

1

ALU LU

ZERO RESULT

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

MUX

1

ADDE DER

RESULT

ADDE DER

RESULT

PC PC MUX

1

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[5-0] 0]

<< 2

CON TROL

INSTRUCTI CTION ON[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ, D,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2

MUX

1

JUMP

<< 2

I[25-0] 0] JMP ADDRESS [25-0] 0] PC+4 4 [31-28] 8] JMP ADDRESS [31-0] 0]

Src: TSR, Cummings, KFR

Computer Program

• MIPS (example RISC) architecture
• Architecture
• Instruction Set
• Programming Resources (registers)
• View of memory (how to read and write it)

10

Label: addi r8, r8, -4 sw r0, 0(r8) bne r3, r0, Label 00400000: 2108fffc ; 00400004: ac000000 ; 00400008: 1400fffd ;

Assembly PC : Instruction

Simple Single Cycle CPU

• Assume each instruction executes in a single cycle
• Instruction Format – MIPS RISC Instructions.
• Fixed instruction size (all instructions are 4 bytes (32 bits)).
• Load/Store, Compute and Control

11

R -Type Opcode Rs Rt Rd Shift (shamt) funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I-Type Opcode Rs Rt Immediate 6 bits 5 bits 5 bits 12 bits J Type Opcode Rs Rt Rd Sa Funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

e.g. add, sub, sll, … add r6, r2, r3 e.g. ori, andi, bne, ld, st, … ld r6, 0x100(r7) bne r3, r0, target e.g. jr, jalr jr target

CPU Components – Single Cycle Execution

Assumptions:

• Every machine language instruction happens in 1 Clock Cycle
• MIPS architecture
• Mic

icroproces

• processor

sor wi without hout int nter erlocked locked pip ipeli line ne stages ges

• reg-reg architecture: all operands must be in registers (total 32)
• 3 Instruction Formats; each instruction 32 bits long
• 1. R-type: all data in registers (most arithmetic and logical)

e.g. add $s1, $s2, $s3

• 2. I-type: branches, memory transfers, constants

e.g. beq $s1, $s2, Label; lw $s1, 32($s2)

• 3. J-type: jumps and calls

e.g. j Label;

12

17 18 16 32 000000 10001 10010 10000 00000 100000

add $s0, $s1, $s2

Src: TSR, Cummings, KFR

13

R-type Instruction: reg-reg ALU ops (e.g. add, and)

OPCO CODE = 0 RT RT RD RD FUNCT CT = 32 32 or

• r 34

34 RS RS

R-ty type pe In Inst struction ruction

31 31-26 26 25 25-21 21 20 20-16 16 15 15-11 11 5-0 So Sour urce ce Re Register ister 1 (attached to “Read Register 1” input) So Sour urce ce Re Register ister 2 (attached to “Read Register 2” input) De Destin stination ation Re Register ister (attached to “Write Register” input) Te Tells lls op

• peratio

ration n to

• be

be pe performed rformed Te Tells lls sp specific cific va variant riant of

• f op
• peration

ration (e (e.g .g. . add dd/sub /sub ha have ve sa same me op

• pcode)
• de)

Sh Shif ift amo moun unt t (f (for

• r

sl sll, l, sr srl l etc.) .)

AD ADD D r5 r5, r7 , r7, r2 , r2 AD ADD D RD RD, , RS RS, RT , RT

10 10-6 shamt

Src: TSR, Cummings, KFR

14

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

MUX

1

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2

MUX

1

ALU LU

ZERO RESULT

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

MUX

1

ADDE DER

RESULT

ADDE DER

RESULT

PC PC MUX

1

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[5-0] 0]

<< 2

CON TROL

INSTRUCTIO TION[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ, D,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

St Step ep 1 (R (R-type): type): Fet etch h inst nstruction ruction an and d ad advan vance ce PC

15

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

MUX

1

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2

ALU LU

RESULT

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

MUX

1

ADDE DER

RESULT

ADDE DER

RESULT

PC PC MUX

1

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTI CTION ON[5-0] 0]

<< 2

CON TROL

INSTRUCTIO TION[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ, D,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

St Step ep 2 (R (R-type): type): Rea ead d tw two r

• regis

egisters ters an and set et con

• ntr

trol

• l signa

gnals ls

ZERO

MUX

1

16

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

MUX

1

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2

MUX

1

ALU LU

RESULT

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

MUX

1

ADDE DER

RESULT

ADDE DER

RESULT

PC PC MUX

1

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[5-0] 0]

<< 2

CON TROL

INSTRUCTIO TION[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ, D,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

St Step ep 3 (R (R-type): type): Per erform form th the e ALU LU op

• per

eration ation

ZERO

17

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

MUX

1

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2

MUX

1

ALU LU

RESULT

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

MUX

1

ADDE DER

RESULT

ADDE DER

RESULT

PC PC MUX

1

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTI CTION ON[5-0] 0]

<< 2

CON TROL

INSTRUCTIO TION[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ, D,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

St Step ep 4 (R (R-type): type): Write te res esult ult to to re register ister

ZERO

18

OPCO CODE = 35 35 or

• r 43

43 RT RT RS RS

St Stor

• re

e In Inst struction ruction

31 31-26 26 25 25-21 21 20 20-16 16 15 15-0 Ba Base se Add ddress ress Re Register ister (attached to “Read Register 1” input) So Sour urce ce re regis ister ter wh whos

• se va

value lue wi will ll be be st stor

• red

ed to me

• memory

mory (attached to “Read Register 2” input) Co Cons nstant ant of

• ffs

fset (a (added dded to the

• the ba

base se add ddress ress in in RS RS)

OFFSET ET

I-Type: Store Instruction

Te Tells lls op

• perat

ration ion to

• be

be pe performed rformed

SW SW r0 r0, 32( , 32(r5) r5)

SW SW RT, #( RT, #(RS) RS) No Note te: sa : same me as as x x86 86 MO MOV [e V [ebx+32 bx+32], ], ea eax x

19

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

MUX

1

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2

MUX

1

ALU LU

ZERO RESULT

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

MUX

1

ADDE DER

RESULT

ADDE DER

RESULT

PC PC MUX

1

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[5-0] 0]

<< 2

CON TROL

INSTRUCTIO TION[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ, D,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

St Step ep 1 (s (store tore): ): Fet etch h inst nstruction ruction an and d ad advan vance ce PC

MUX

1

20

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

ADDE DER

RESULT

ADDE DER

RESULT

PC PC MUX

1

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[5-0] 0]

<< 2

CON TROL

INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2 INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16]

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

ALU LU

RESULT ZERO

MUX

1

St Step ep 2 (s (store tore): ): Rea ead d reg egister ister va values lues an and d set et co control trol signals ignals

MUX

1

MUX

1

21

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

ADDE DER

RESULT

ADDE DER

RESULT

PC PC MUX

1

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[5-0] 0]

<< 2

CON TROL

INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ, D,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2 INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16]

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

ALU LU

RESULT ZERO

MUX

1

St Step ep 3 (s (store tore): ): Co Compute ute th the e ad address ress

MUX

1

MUX

1

22

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

ADDE DER

RESULT

ADDE DER

RESULT

PC PC MUX

1

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[5-0] 0]

<< 2

CON TROL

INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ, D,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2 INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16]

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

ALU LU

RESULT ZERO

MUX

1

St Step ep 4 (s (store tore): ): Write te th the e va value lue to to mem memor

• ry

MUX

1

MUX

1

23

OPCO CODE = 4 o 4 or r 5 RT RT RS RS

BEQ EQ/BNE /BNE In Inst struction ruction

31 31-26 26 25 25-21 21 20 20-16 16 15 15-0 So Sour urce ce Re Register ister 1 (attached to “Read Register 1” input) So Sour urce ce re regis ister ter 2 2 (attached to “Read Register 2” input) Wo Word rd Off ffset, set, wh whic ich h we we mu mult ltiply iply by by 4 (v 4 (via ia <<2) 2) to ge

• get Bi

Bit Off ffset set, , the hen n add dd to PC

• PC+4

+4 to ge

• get the

he add ddress ress of

• f the

he in inst struction ruction to

• wh

whic ich h we we br branch nch if if RS RS == = RT RT) “PC-relative address”

BRANCH TARGET’S OFFSET

I-Type: Conditional Branch

BE BEQ S Source1,

• urce1, So

Source2, urce2, O Off ffset set BE BEQ $r $r7, 7, r2 r20, 0, 10 100 4 4 7 2 7 20 0 2 25

24

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

MUX

1

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2

MUX

1

ALU LU

ZERO RESULT

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

MUX

1

ADDE DER

RESULT

ADDE DER

RESULT

PC PC MUX

1

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[5-0] 0]

<< 2

CON TROL

INSTRUCTIO TION[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ, D,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

St Step ep 1 (b (beq): eq): Fet etch h inst nstruction ruction an and d ad advance vance PC

MUX

1

25

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

MUX

1

ADDE DER

RESULT

ADDE DER

RESULT

PC PC

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[5-0] 0]

<< 2

CON TROL

INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ, D,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2 INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16]

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

ALU LU

RESULT ZERO

MUX

1

St Step ep 2 (b (beq): eq): Rea ead d regis egister ter va values lues an and d set et con

• ntr

trol

• l signals

ignals

MUX

1

MUX

1

26

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

MUX

1

ADDE DER

RESULT

ADDE DER

RESULT

PC PC

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[5-0] 0]

<< 2

CON TROL

INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ, D,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2 INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16]

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

ALU LU

RESULT ZERO

MUX

1

St Step ep 3 ( (beq eq): ): Co Comp mpare are regist egisters, ers, ca calcula culate te branch anch ta target, et, an and d choose

• ose new

ew PC

MUX

1

MUX

1

27

OPCO CODE = 2 o 2 or r 3

JMP MP/JA /JAL L In Inst struction ruction

31 31-26 26 25 25-0 Ac Actual ual Ad Address dress (i (in n wo word rds) s) wh whic ich h we we mu mult ltiply iply by by 4 (< 4 (<<2) <2) to ge

• get 28

28-Bit Bit Add ddress, ress, the hen n con

• ncaten

catenate ate to up

• uppe

per r 4 bi 4 bits s of

• f PC

PC+4 4 to ge

• get the

he 32 32-bit bit add ddress ress of

• f in

inst struction ruction to

• wh

whic ich h we we br branch nch un uncon

• ndi

ditionally tionally

BR BRANCH CH TA TARGET GET ADDRESS SS

J-Type: Unconditional Branch

J O J Off ffset set J 10 J 1000 000 2 2 2 250 500

28

INSTR STRUCT UCTION ION MEMOR MORY

READ ADDRESS INSTRUCTIO TION [31-0] 0]

MUX

1

MUX

1

ALU LU

ZERO RESULT

DATA TA MEMOR MORY

ADDRESS WRITE TE DATA READ DATA

MUX

1

ADDE DER

RESULT

ADDE DER

RESULT

PC PC MUX

1

4

Sign Extend nd

ALU ALU CONTROL OL

INSTRUCTIO TION[15 15-0] 0] INSTRUCTIO TION[5-0] 0]

<< 2

CON TROL

INSTRUCTI CTION ON[31 31-26] 26] INSTRUCTIO TION[25 25-21] 21] INSTRUCTIO TION[20 20-16] 16] INST[15 15-11] 11] BRANCH REG_DST REG_WRITE RITE ALU_SR SRC ALU_OP OP MEM_READ, D,ME MEM_ M_WRI WRITE TE MEM_TO_R O_REG

REGIST GISTERS ERS

READ REGISTER R 1 READ REGISTER R 2 WRITE TE REGISTER WRITE TE DATA READ DATA 1 READ DATA 2

MUX

1

JUMP

<< 2

I[25-0] 0] JMP ADDRESS [25-0] 0] PC+4 4 [31-28] 8] JMP ADDRESS [31-0] 0]

Sing ngle le-Cy Cycle le Datapath apath with th Supp pport

• rt for the Jump

mp Instruc tructio ion