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CSE140 - Processors 8-bit adder Edited file from Bryan Chin http://www.megaprocessor.com/ 1

Navigation Check • Simple (RISC) Processor 2

Simplified Digital Computer Instruction Store Register File Execute Control ALU Memory Multiply/Divide 3

Simplified Digital Computer Instruction Types Instruction Store • Load Register • Store PC File • Control Flow • Execute Execute Control ALU Memory Add, logic, shift Multiply/Divide 4

SRAM (single port) WL B+ B- • 32 rows, 32 columns 32 columns • Can read or write one row at a time Memory Cells (32 bits wide) Memory Cells Decoder 32 rows • Decoder – takes in 5 bits, generates 1 of 32 (one-hot output) Memory Cells Memory Cells Sense Amp Addr[4:0] Write Driver Processor Register file WE* MIPS I - 32 registers, 32 bits Data[31:0] Need to read 2 operands and write 1 3 ports 5

Register File – smallish SRAM with more ports WL B+ B- Processor Register file • 32 columns MIPS I - 32 registers, 32 bits • Memory Cells Need to read 2 operands and write 1 • Memory Cells 3 ports • Decoder Decoder Decoder Modern processor register files may have • 32 rows lots of ports (e.g 14 R and 7 W) Memory Cells Memory Cells Make an array of Sense Amp these Sense Amp WAddr[4:0] Write Driver WE * rdA[31:0] AddrA[4] writeData[31:0] rdB[31:0] AddrB[4] 6

Row Decoder • 5->32 decoder choses which row • One decoder per port Addr[0] Addr[4] Addr[2] Addr[1] Addr[3] 7

A register file is 128 bits wide and contains a total of 1 KB of storage. How many address bits will be required by the row decoder? A. 10 bits B. 9 bits C. 64 bits D. 6 bits E. None of the above * - B means byte, b means bit 8

PC+4 4 [31-28] 8] JMP ADDRESS [31-0] 0] 4 RESULT 0 1 ADDE DER MUX MUX 0 1 RESULT ADDE DER I[25-0] 0] JMP ADDRESS [25-0] 0] << 2 << 2 PC PC BRANCH JUMP REG_DST INSTRUCTI CTION ON[31 31-26] 26] CON TROL MEM_TO_R MEM_READ, D,ME MEM_ M_WRI WRITE TE REG_WRITE RITE ALU_SR SRC ALU_OP OP O_REG INSTRUCTIO TION[25 25-21] 21] READ READ ADDRESS REGISTER R 1 READ INSTRUCTIO TION[20 20-16] 16] DATA 1 READ ZERO REGISTER R 2 INSTR STRUCT UCTION ION ALU LU 0 REGIST GISTERS ERS READ MEMOR MORY ADDRESS RESULT DATA WRITE TE MUX READ REGISTER 0 DATA 2 INST[15 15-11] 11] INSTRUCTIO TION 1 WRITE TE DATA TA MUX [31-0] 0] DATA MEMOR MORY 1 WRITE TE DATA Sign INSTRUCTIO TION[15 15-0] 0] Extend nd ALU ALU 0 1 MUX CONTROL OL INSTRUCTIO TION[5-0] 0] Src: TSR, Cummings, KFR 9

Computer Program • MIPS (example RISC) architecture • Architecture Instruction Set • Programming Resources (registers) • View of memory (how to read and write it) • Assembly PC : Instruction Label: addi r8, r8, -4 00400000: 2108fffc ; sw r0, 0(r8) 00400004: ac000000 ; bne r3, r0, Label 00400008: 1400fffd ; 10

Simple Single Cycle CPU • Assume each instruction executes in a single cycle • Instruction Format – MIPS RISC Instructions. Fixed instruction size (all instructions are 4 bytes (32 bits)). • Load/Store, Compute and Control • R -Type e.g. add, sub, sll , … Opcode Rs Rt Rd Shift (shamt) funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add r6, r2, r3 e.g. ori, andi, bne, ld, st , … I-Type ld r6, 0x100(r7) Opcode Rs Rt Immediate 6 bits 5 bits 5 bits 12 bits bne r3, r0, target J Type e.g. jr, jalr Opcode Rs Rt Rd Sa Funct jr target 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 11

CPU Components – Single Cycle Execution Assumptions: Every machine language instruction happens in 1 Clock Cycle • MIPS architecture • M ic icroproces oprocessor sor wi without hout i nt nter erlocked locked p ip ipeli line ne s tages ges • reg-reg architecture: all operands must be in registers (total 32) • 3 Instruction Formats; each instruction 32 bits long • 1. R-type: all data in registers (most arithmetic and logical) e.g. add $s1, $s2, $s3 2. I-type: branches, memory transfers, constants e.g . beq $s1, $s2, Label; lw $s1, 32($s2) 3. J-type: jumps and calls e.g. j Label; 000000 10001 10010 10000 00000 100000 add $s0, $s1, $s2 0 17 18 16 0 32 Src: TSR, Cummings, KFR 12

R-type Instruction: reg-reg ALU ops (e.g. add, and) Tells Te lls op operatio ration n to o Te Tells lls sp specific cific va variant riant of of op operation ration be pe be performed rformed (e (e.g .g. . add dd/sub /sub ha have ve sa same me op opcode) ode) R-ty type pe OPCO CODE shamt RS RS RT RT RD RD FUNCT CT In Inst struction ruction = 0 = 32 32 or or 34 34 31 31-26 26 25 25-21 21 20-16 20 16 15-11 15 11 5-0 10 10-6 ADD AD D r5 r5, r7 , r7, r2 , r2 Shif Sh ift amo moun unt t (f (for or sll, sl l, sr srl l etc.) .) ADD AD D RD RD, , RS RS, RT , RT So Sour urce ce Re Register ister 2 (attached to “Read De Destin stination ation Re Register ister So Sour urce ce Re Register ister 1 Register 2” input) (attached to “Write (attached to “Read Register” input) Register 1” input) Src: TSR, Cummings, KFR 13

4 RESULT 0 ADDE DER MUX 1 RESULT ADDE DER << 2 PC PC BRANCH REG_DST INSTRUCTIO TION[31 31-26] 26] CON TROL MEM_TO_R MEM_READ, D,ME MEM_ M_WRI WRITE TE REG_WRITE RITE ALU_SR SRC ALU_OP OP O_REG INSTRUCTIO TION[25 25-21] 21] READ READ ADDRESS REGISTER R 1 READ INSTRUCTIO TION[20 20-16] 16] DATA 1 READ ZERO REGISTER R 2 INSTR STRUCT UCTION ION ALU LU 0 REGIST GISTERS ERS READ MEMOR MORY ADDRESS RESULT DATA WRITE TE MUX READ REGISTER 0 DATA 2 INST[15 15-11] 11] INSTRUCTIO TION 1 WRITE TE DATA TA MUX [31-0] 0] DATA MEMOR MORY 1 WRITE TE DATA Sign INSTRUCTIO TION[15 15-0] 0] Extend nd ALU ALU 0 1 MUX CONTROL OL INSTRUCTIO TION[5-0] 0] St Step ep 1 (R (R-type): type): Fet etch h inst nstruction ruction an and d ad advan vance ce PC 14

4 RESULT 0 ADDE DER MUX 1 RESULT ADDE DER << 2 PC PC BRANCH REG_DST INSTRUCTIO TION[31 31-26] 26] CON TROL MEM_TO_R MEM_READ, D,ME MEM_ M_WRI WRITE TE REG_WRITE RITE ALU_SR SRC ALU_OP OP O_REG INSTRUCTIO TION[25 25-21] 21] READ READ ADDRESS REGISTER R 1 READ INSTRUCTIO TION[20 20-16] 16] DATA 1 READ ZERO REGISTER R 2 INSTR STRUCT UCTION ION ALU LU 0 REGIST GISTERS ERS READ MEMOR MORY ADDRESS RESULT DATA WRITE TE MUX READ REGISTER 0 DATA 2 INST[15 15-11] 11] INSTRUCTIO TION 1 WRITE TE DATA TA MUX [31-0] 0] DATA MEMOR MORY 1 WRITE TE DATA Sign INSTRUCTIO TION[15 15-0] 0] Extend nd ALU ALU 0 1 MUX CONTROL OL INSTRUCTI CTION ON[5-0] 0] Step St ep 2 (R (R-type): type): Rea ead d tw two r o regis egisters ters an and set et con ontr trol ol signa gnals ls 15

4 RESULT 0 ADDE DER MUX 1 RESULT ADDE DER << 2 PC PC BRANCH REG_DST INSTRUCTIO TION[31 31-26] 26] CON TROL MEM_TO_R MEM_READ, D,ME MEM_ M_WRI WRITE TE REG_WRITE RITE ALU_SR SRC ALU_OP OP O_REG INSTRUCTIO TION[25 25-21] 21] READ READ ADDRESS REGISTER R 1 READ INSTRUCTIO TION[20 20-16] 16] DATA 1 READ ZERO REGISTER R 2 INSTR STRUCT UCTION ION ALU LU 0 REGIST GISTERS ERS READ MEMOR MORY ADDRESS RESULT DATA WRITE TE MUX READ REGISTER 0 DATA 2 INST[15 15-11] 11] INSTRUCTIO TION 1 WRITE TE DATA TA MUX [31-0] 0] DATA MEMOR MORY 1 WRITE TE DATA Sign INSTRUCTIO TION[15 15-0] 0] Extend nd ALU ALU 0 1 MUX CONTROL OL INSTRUCTIO TION[5-0] 0] St Step ep 3 (R (R-type): type): Per erform form th the e ALU LU op oper eration ation 16

4 RESULT 0 ADDE DER MUX 1 RESULT ADDE DER << 2 PC PC BRANCH REG_DST INSTRUCTIO TION[31 31-26] 26] CON TROL MEM_TO_R MEM_READ, D,ME MEM_ M_WRI WRITE TE REG_WRITE RITE ALU_SR SRC ALU_OP OP O_REG INSTRUCTIO TION[25 25-21] 21] READ READ ADDRESS REGISTER R 1 READ INSTRUCTIO TION[20 20-16] 16] DATA 1 READ ZERO REGISTER R 2 INSTR STRUCT UCTION ION ALU LU 0 REGIST GISTERS ERS READ MEMOR MORY ADDRESS RESULT DATA WRITE TE MUX READ REGISTER 0 DATA 2 INST[15 15-11] 11] INSTRUCTIO TION 1 WRITE TE DATA TA MUX [31-0] 0] DATA MEMOR MORY 1 WRITE TE DATA Sign INSTRUCTIO TION[15 15-0] 0] Extend nd ALU ALU 0 1 MUX CONTROL OL INSTRUCTI CTION ON[5-0] 0] St Step ep 4 (R (R-type): type): Write te res esult ult to to re register ister 17

I-Type: Store Instruction Tells Te lls op operat ration ion to o be pe be performed rformed St Stor ore e OPCO CODE RS RS RT RT OFFSET ET In Inst struction ruction = 35 35 or or 43 43 31-26 31 26 25-21 25 21 20-16 20 16 15-0 15 Base Ba se Add ddress ress Re Register ister So Sour urce ce re regis ister ter Co Cons nstant ant of offs fset (attached to “Read wh whos ose va value lue wi will ll be be (a (added dded to the o the ba base se Register 1” input) st stor ored ed to me o memory mory add ddress ress in in RS RS) (attached to “Read Register 2” input) SW r0 SW r0, 32( , 32(r5) r5) No Note te: sa : same me as as x x86 86 SW RT, #( SW RT, #(RS) RS) MO MOV [e V [ebx+32 bx+32], ], ea eax x 18