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gelFORTH | A Forth for interactive hardware design . Andreas Wagner - PowerPoint PPT Presentation

Feb 24, 2023 •24 likes •404 views

gelFORTH | A Forth for interactive hardware design . Andreas Wagner andreas.wagner@lowfatcomputing.org http://www.0xFF.in @lowfatcomputing The Cypress PSoC 5LP ( What is it?) an SoC with: an ARM Cortex M3 a Universal Digital Block

  1. gelFORTH | A Forth for interactive hardware design . Andreas Wagner andreas.wagner@lowfatcomputing.org http://www.0xFF.in @lowfatcomputing

  2. The Cypress PSoC 5LP ( What is it?) an SoC with: ● an ARM Cortex M3 ● a Universal Digital Block “UDB” array – reconfjgurable logic & routing – something like a CPLD ● a Universal Analog Block “UAB” array – reconfjgurable logic & routing ● Proprietary Windows Only Toolchain :( ● Routing fabric is undocumented :(

  3. The Cypress PsoC 5LP ( block diagram)

  4. Interactive Hardware Design. Why? ● Electronics multi-tool with loadable “hardware” modules and good performance for them. ● Free/Open Source. No MS Windows IDE necessary. ● Rapidly and interactively explore hardware designs with the same code used to write software.

  5. → Forth Gates ( has anyone done it?)

  10. Testra’s VHDL in Forth It’s a special purpose lexicon… ...Perhaps it need not be so special.

  12. Parallel Forth ( new wrapper; same GREAT taste!)

  13. Verilog is parallel, Forth HDL as just parallel Forth?! ● Uses an alternate set of primitive words ● Same high level Forth code on top ...but it runs in parallel.

  14. Ladder Logic or String Diagrams

  15. When WORDs are independent they are in-parallel: They are parallel and are leveraging Boolean OR

  16. Where WORDs have dependencies they are in-series: ● The parameters pile up on the stack ● Therefore they must be dealt with in-order.

  17. ( another reason to minimize stack effects!)

  18. designing the alternate primitive wordset...

  19. an XNOR gate : XNOR ( XNOR gate from pins 1.6, 1.7 to blue led at pin 2.1) P1.6 @ , P1.7 @ , ( DSI → routing tiles → pi tiles) | ( compiles a wire) P1.6 @ ~ , P1.7 @ ~ , ( DSI → routing tiles → pi tiles) | ( compiles a parallel wire) P2.1 ! ( build route to the blue led) ;

  20. an XNOR gate : XNOR ( route the output of input pins through…) P1.6 @ , P1.7 @ , ( DSI → routing tiles → pi tiles) | P1.6 @ ~ , P1.7 @ ~ , ( DSI → routing tiles → pi tiles) | P2.1 ! ;

  21. Port Pins reference VARIABLE data ● Indicate a variable data reference with @ ● Compile a variable data reference with !

  22. synth alternate wordset: @ ! we can reference a thing… …but we’ll have to build a route to it ourselves.

  23. an XNOR gate : XNOR ( compile NOT gates into AND array) P1.6 @ , P1.7 @ , ( no complement bits compiled) | P1.6 @ ~ , P1.7 @ ~ , ( compile complement bits) | P2.1 ! ;

  24. an XNOR gate : XNOR ( compile YES gates into AND array) P1.6 @ , P1.7 @ , ( compile truth bits) | P1.6 @ ~ , P1.7 @ ~ , ( compile truth bits) | P2.1 ! ;

  25. an XNOR gate : XNOR ( compile bits to the OR-array ) P1.6 @ , P1.7 @ , | ( compiles a wire) P1.6 @ ~ , P1.7 @ ~ , | ( compiles a parallel wire) P2.1 ! ;

  26. an XNOR gate : XNOR ( compile bits to the OR-array ) P1.6 @ , P1.7 @ , | ( compiles a wire) P1.6 @ ~ , P1.7 @ ~ , | ( compiles a parallel wire) P2.1 ! ;

  27. an XNOR gate : XNOR ( macrocell and PLD output) P1.6 @ , P1.7 @ , | ( compiles a wire) P1.6 @ ~ , P1.7 @ ~ , | ( compiles a parallel wire) P2.1 ! ;

  28. synth parallel wordset: ALLOT Maneuvering

  29. Logic Synth words, analogous to regular Forth words ● we’re compiling regular Forth to parallel Forth ● synth words have the same names ● …but they compile to the UBD array instead of the Flash or RAM dictionary.

  30. synth alternate wordset: ALLOT Maneuvering ● the addressing scheme is very consistent ● manipulate the addresses to maneuver

  31. ALLOT revolves around YES, NOT, AND, OR ● Logic can spill over into other PLD’s, UDB’s, UDB Pairs, and UDB Banks. ● Routes are also ALLOTed.

  32. Routing is short-circuiting. ● PSoC 5LP routing works by short-circuiting ● Shorting in-series gates: AND-gates ● Shorting in-parallel wires: OR-gates

  33. Routing as logic synthesis?

  34. Placement ● How can we rearrange Boolean expressions? ● By way of the commutative, associative, distributive properties!

  35. Done & To be done Done: ● PLD synthesis ● routing fabric PI, HS, HC, VS tiles understood To Do: ● Parallel logic synthesis (in-progress) ● Universal Analog Blocks (in-progress) ● Hard IP blocks ● HV tiles (in-progress)

  36. Questions , Comments , World Views?

  37. Thanks for listening ! ( – Follow the project on hackaday.io!)

  38. references. ● https://www.reddit.com/r/Forth/comments/58 7dfh/high_stack_fjnegrain_concurrency/d8yb gi0/ ● https://www.reddit.com/r/Forth/comments/59 9lb4/symbols_for_stack_operators/d9e7vqg/? context=9999 ● http://www.forth.org/fd/FD-V21N1,2.pdf#pag e=21

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