Course Introduction Foundations of Global Networked Computing: - - PowerPoint PPT Presentation

Foundations of Global Networked Computing: Building a Modern Computer From First Principles

IWKS 3300: NAND to Tetris Spring 2019 John K. Bennett

This course is based upon the work of Noam Nisan and Shimon Schocken. More information can be found at (www.nand2tetris.org).

Course Introduction

Course at a Glance

Objectives:  Understand how hardware and software systems are built, and how they work together  Learn how to break complex problems into simpler ones  Learn how large scale development projects are planned and executed  Have some fun in the process Methodology:  Build a complete, general-purpose working computer system  Play and experiment with this computer, at any level of interest

Some Course Details

 12 projects, generally intended to be completed by one or two students working together (pair programming)  Four hardware projects that are designed and developed using a logic design program (LogicCircuit), saved as HDL (Hardware Description Language), and tested using a hardware simulator and test script (part of the N2T tool suite).*  Eight software projects: one in “Hack” assembly, two in “Jack” (a Java-like high level language), and five software projects (Hack Assembler, Virtual Machine (two projects), and Jack Compiler (two projects)).  The five non-Hack/Jack software projects must be completed using C# / Visual Studio 2017 Community. I will also use this combination for all in-class examples.

* The HDL can be translated into Structural VHDL using local software, synthesized using Xilinx Vivaldo, and executed on the Digilent BASYS 3/Artix 7 FPGA board.

Some Course Details

 Projects methodology:  Design (API) + test materials are given  Implementation completed using pair programming  Tools: simulators, tutorials, test scripts (from book authors), LogicCircuit (a free program for circuit design and simulation with JKB mods), Xilinx Vivaldo (a modern FPGA design suite), JKB’s HDL to VHDL translator, some VHDL scaffolding for screen, keyboard, etc., file comparators, etc.  Book: The Elements of Computing Systems: Building a Modern Computer from First Principles by Noam Nisan and Shimon Schocken (first 5 chapters locally modified)

Course Trajectory (in reverse)

Assembler

Chapter 6

H.L. Language & Operating Sys.

abstract interface

Compiler

Chapters 10 - 11

VM Translator

Chapters 7 - 8

Computer Architecture

Chapters 4 - 5

Gate Logic

Chapters 1 - 3

Electrical Engineering Physics Virtual Machine

abstract interface

Software hierarchy

Assembly Language

abstract interface

Hardware hierarchy

Machine Language

abstract interface

Hardware Platform

abstract interface

Chips & Logic Gates

abstract interface

Human Thought Abstract design

Chapters 9, 12

(Abstraction–implementation paradigm)

Application Level: a simple game, e.g., Pong

Ball abstraction Bat abstraction

The Big Picture

Assembler

Chapter 6

H.L. Language & Operating Sys.

abstract interface

Compiler

Chapters 10 - 11

VM Translator

Chapters 7 - 8

Computer Architecture

Chapters 4 - 5

Gate Logic

Chapters 1 - 3

Electrical Engineering Physics Virtual Machine

abstract interface

Software hierarchy

Assembly Language

abstract interface

Hardware hierarchy

Machine Language

abstract interface

Hardware Platform

abstract interface

Chips & Logic Gates

abstract interface

Human Thought Abstract design

Chapters 9, 12

High-level programming (in “Jack,” a Java-like language)

/** A Graphic Bat for a Pong Game */ class Bat { field int x, y; // screen location of the bat's top-left corner field int width, height; // bat's width & height // The class constructor and most of the class methods are omitted /** Draws (color=true) or erases (color=false) the bat */ method void draw(boolean color) { do Screen.setColor(color); do Screen.drawRectangle(x,y,x+width,y+height); return; } /** Moves the bat one step (4 pixels) to the right. */ method void moveR() { do draw(false); // erase the bat at the current location let x = x + 4; // change the bat's X-location // but don't go beyond the screen's right border if ((x + width) > 511) { let x = 511 - width; } do draw(true); // re-draw the bat in the new location return; } }

Ball abstraction Bat abstraction

Typical call to an OS method

Operating System Level (Jack OS, written in Jack)

/** An OS-level screen driver that abstracts the computer's physical screen */ class Screen { static boolean currentColor; // the current color // The Screen class is a collection of methods, each implementing one // abstract screen-oriented operation. Most of this code is omitted. /** Draws a rectangle in the current color. */ // the rectangle's top left corner is anchored at screen location (x0,y0) // and its width and length are x1 and y1, respectively. function void drawRectangle(int x0, int y0, int x1, int y1) { var int x, y; let x = x0; while (x < x1) { let y = y0; while(y < y1) { do Screen.drawPixel(x,y); let y = y+1; } let x = x+1; } } }

Ball abstraction Bat abstraction

The Compiler

Assembler

Chapter 6

H.L. Language & Operating Sys.

abstract interface

Compiler

Chapters 10 - 11

VM Translator

Chapters 7 - 8

Computer Architecture

Chapters 4 - 5

Gate Logic

Chapters 1 - 3

Electrical Engineering Physics Virtual Machine

abstract interface

Software hierarchy

Assembly Language

abstract interface

Hardware hierarchy

Machine Language

abstract interface

Hardware Platform

abstract interface

Chips & Logic Gates

abstract interface

Human Thought Abstract design

Chapters 9, 12

Modern Compilation Uses a Virtual Machine

How Compilation Works

Observations:  Modularity  Abstraction / implementation interplay  Each level’s implementation uses abstract services from the level below.

parsing Code generation Source code if (x + width) > 511

Abstraction

push x push width add push 511 gt Intermediate VM code

Implementation Syntax Analysis Parse Tree Semantic Synthesis

width x + 511 >

The Virtual Machine (our VM is modeled after Java’s JVM)

if ((x+width)> 511) { let x=511-width; }

// VM implementation push x // s1 push width // s2 add // s3 push 511 // s4 gt // s5 if-goto L1 // s6 goto L2 // s7 L1: push 511 // s8 push width // s9 sub // s10 pop x // s11 L2: ...

75 450

sp s2

memory (before)

450

...

x width 75

... ...

525 511

sp

1

sp

511 450

sp s4 s5 s9

61

sp s10

450

...

x width 61

... ...

memory (after)

Translating VM Code

Assembler

Chapter 6

H.L. Language & Operating Sys.

abstract interface

Compiler

Chapters 10 - 11

VM Translator

Chapters 7 - 8

Computer Architecture

Chapters 4 - 5

Gate Logic

Chapters 1 - 3

Electrical Engineering Physics Virtual Machine

abstract interface

Software hierarchy

Assembly Language

abstract interface

Hardware hierarchy

Machine Language

abstract interface

Hardware Platform

abstract interface

Chips & Logic Gates

abstract interface

Human Thought Abstract design

Chapters 9, 12

Translating VM Code to Machine Code

Executing Machine Code

Assembler

Chapter 6

H.L. Language & Operating Sys.

abstract interface

Compiler

Chapters 10 - 11

VM Translator

Chapters 7 - 8

Computer Architecture

Chapters 4 - 5

Gate Logic

Chapters 1 - 3

Electrical Engineering Physics Virtual Machine

abstract interface

Software hierarchy

Assembly Language

abstract interface

Hardware hierarchy

Machine Language

abstract interface

Hardware Platform

abstract interface

Chips & Logic Gates

abstract interface

Human Thought Abstract design

Chapters 9, 12

Machine Language Semantics (on the Hack platform)

Code syntax

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 1 1 1 Instruction code (0=“address” inst.) Address ALU

• peration code

(M-1) Destination Code (M) Jump Code (no jump)

Code semantics, as interpreted by the Hack hardware platform

Instruction code (1=“compute” inst.) 0000000000000000 1111110111001000 @0 M=M-1

 We need a hardware architecture that implements these semantics  The hardware platform must be designed to:

• Decode instructions, and then,
• Execute them.

Computer Architecture (Hack platform, approx.)

 A typical Harvard Architecture machine (not Von Neumann; why?)

Data Memory (M) ALU Instruction Memory instruction A D M

Program Counter

address of next instruction data in data out RAM(A)

load on jump

Building Hardware

Assembler

Chapter 6

H.L. Language & Operating Sys.

abstract interface

Compiler

Chapters 10 - 11

VM Translator

Chapters 7 - 8

Computer Architecture

Chapters 4 - 5

Gate Logic

Chapters 1 - 3

Electrical Engineering Physics Virtual Machine

abstract interface

Software hierarchy

Assembly Language

abstract interface

Hardware hierarchy

Machine Language

abstract interface

Hardware Platform

abstract interface

Chips & Logic Gates

abstract interface

Human Thought Abstract design

Chapters 9, 12

Logic Design

 Combinational (combinatorial) logic (leading to an ALU)  Sequential (clocked) logic (leading to a RAM, PC, Registers)  Putting the whole thing together (leading to a Computer) Using … Nand gates

NAND Truth Table

Implementing Gate Logic

Xor a b

• ut

0 0 0 0 1 1 1 0 1 1 1 0 a b out

Interface  Hardware is an inter-connected set of chips (integrated circuits).  Chips are made of simpler chips, all the way down to elementary logic gates  Logic gate = hardware element that implements a certain Boolean function  Every chip and gate has an interface, specifying WHAT it is doing, and an implementation, specifying HOW it is doing it.

And And Not Or

• ut

a b

Not

A (not very good) implementation

Hardware Description Language (HDL)

And And Not Or

• ut

a b

Not

CHIP Xor { IN a,b; OUT out; PARTS: Not(in=a,out=Nota); Not(in=b,out=Notb); And(a=a,b=Notb,out=w1); And(a=Nota,b=b,out=w2); Or(a=w1,b=w2,out=out); }

 … using only NAND gates

A Better XOR Implementation Why is this better?

How Will We Create These HDL Files?

CHIP Nand { IN a, b; OUT out; PARTS: Nand2 (x1 = a, x2 = b, q = out); }

How Will We Create These HDL Files?

//Xor.hdl CHIP Xor { IN a, b; OUT; PARTS: Nand (a = a, b = b, out = U0out); Nand (a = a, b = U0out, out = U1out); Nand (a = U0out, b = b, out = U2out); Nand (a = U1out, b = U2out, out =

• ut);

}

“SaveAsHDL”

How Will We Test These HDL Files?

//Xor.hdl CHIP Xor { IN a, b; OUT; PARTS: Nand (a = a, b = b, out = U0out); Nand (a = a, b = U0out, out = U1out); Nand (a = U0out, b = b, out = U2out); Nand (a = U1out, b = U2out, out =

• ut);

}

“Load Chip”

How Will We Test These HDL Files?

// Xor.tst load Xor.hdl,

• utput-file Xor.out,

compare-to Xor.cmp,

• utput-list a%B3.1.3 b%B3.1.3
• ut%B3.1.3;

set a 0, set b 0, eval,

• utput;

set a 0, set b 1, eval,

• utput;

set a 1, set b 0, eval,

• utput;

“Load Script”

How Will We Test These HDL Files?

| a | b | out | | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 |

Xor.cmp

| a | b | out | | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 |

Xor.out

If (Xor.out == Xor.cmp)

Hardware Simulator (LogicCircuit)

Hardware Simulator (Book)

CPU Emulator (Book)

Translating HDL to VHDL (HDL2VHDL)

HDL2VHDL

HDL VHDL (Structural)

Behavioral VHDL and HLS

VHDL (Behavorial) Xilinx Vivaldo HLS (“C”)

Synthesizing VHDL (Vivaldo Webpack)

Executing the Synthesized VHDL in an Artix 7 FPGA (Vivaldo)

The Tour Ends:

Interface Diode Transistor Implementation

0 0 1 0 1 1 1 0 1 1 1 0 a b out

• ut

a b Nand

CMOS Implementation

We will build this in class

Course Overview: Building This World From the Ground Up

Assembler

Chapter 6

H.L. Language & Operating Sys.

abstract interface

Compiler

Chapters 10 - 11

VM Translator

Chapters 7 - 8

Computer Architecture

Chapters 4 - 5

Gate Logic

Chapters 1 - 3

Electrical Engineering Physics Virtual Machine

abstract interface

Software hierarchy

Assembly Language

abstract interface

Hardware hierarchy

Machine Language

abstract interface

Hardware Platform

abstract interface

Chips & Logic Gates

abstract interface

Human Thought Abstract design

Chapters 9, 12

What is Inworks?

Inworks is an initiative of the University of Colorado Denver │ Anschutz Medical Campus that draws together faculty, staff and students from across the two campuses, as well as entrepreneurs and leaders from industry, government, education and the community, to address problems of importance to human society.

• Our mission is to impart skills

and habits of mind that allow people to collaboratively create impactful solutions to human problems.

• We seek to create innovative

solutions to some of the world’s most challenging problems, while in the process creating life- long innovators.

• We do this by scaffolding

collaborative innovation and providing extensive facilities for rapid prototyping.

Inworks: Creating Lifelong Innovators

How Do We Do This?

• Inworks, drawing upon ideas from

modern entrepreneurial practice, was created to provide educational experiences that develop critical intellectual capacities.

• We do this by providing a scaffold for

innovation that integrates empathy, creativity and practicality to match human need with feasibility.

• Through hands-on, human-centered,

team-based projects, we help create experiences that allow individuals to encounter their own creativity, and we show students how to be intentional about the way they work together to solve significant problems.

What is Design Thinking?

• A human-centered process for

creatively developing solutions to complex problems.

• A scaffold for innovation that

integrates empathy, creativity, and practicality to match human need with feasibility.

• Highlights the critical role of

creativity in every human endeavor.

• Extends the design philosophy to

things outside of products.

• Provides a vocabulary for being

intentional about the way we work together to solve significant problems.

Does Inworks Teach This? YES (stay tuned) (and we also try to practice it)

Inworks Programs

• Inworks Courses
• Undergraduate

Certificate

• Undergraduate

Minor

• Graduate

Certificate

• Workshops
• Meetups