Implementation of a noise subtraction algorithm using Verilog HDL - - PowerPoint PPT Presentation

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Implementation of a noise subtraction algorithm using Verilog HDL - - PowerPoint PPT Presentation

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Implementation of a noise subtraction algorithm using Verilog HDL University of Massachusetts, Amherst Department of Electrical & Computer Engineering, Course 559/659 by Perry Levy, Aseem Pangotra, Stephan Stiglmayr and Thomas Kunkel Team

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SLIDE 1

Implementation of a noise subtraction algorithm using Verilog HDL

University of Massachusetts, Amherst Department of Electrical & Computer Engineering, Course 559/659 by Perry Levy, Aseem Pangotra, Stephan Stiglmayr and Thomas Kunkel Team Leader: Prof. Maciej Ciesielski

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SLIDE 2

Noise-subtracting algorithm

Time to frequency transformation Subtraction of magnitudes Distortion correction Frequency to time transformation

Algorithm Algorithm Modules FFT Subtraction In- / Output

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SLIDE 3

Noise-subtracting algorithm

Algorithm Modules Modules FFT Subtraction In- / Output

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SLIDE 4

Noise-subtracting algorithm

Serial data Shifts of 16bits Storing in 1032 x 32bit memory Flushing memory to FFT after

receiving of 256 pairs of data

Algorithm Modules FFT Subtraction In- / Output In- / Output

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SLIDE 5

Noise-subtracting algorithm

State machine

storing data in memory

Flushing memory

Buffering data Emptying buffer

Reset 256 pairs Mem flushed Buffer emptied

Algorithm Modules FFT Subtraction In- / Output In- / Output

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SLIDE 6

Noise-subtracting algorithm

Block Diagram

Data SCLK LRCLK Reset Data Address WR RD Flushing Enable Done Hold Data Real part Imaginary Valid Output

Serial shifter 16bit counter Address generator Buffer Finite state machine 1024 x 32bit RAM

Algorithm Modules FFT Subtraction In- / Output In- / Output

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SLIDE 7

Noise-subtracting algorithm

Parallel input and output of variables 16Bit address, 8Bit data (compatible

to microcontroller)

Preset values when resetting

Algorithm Modules FFT Subtraction In- / Output In- / Output

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SLIDE 8

Noise-subtracting algorithm

Implementation of Radix 2 algorithm Window length 1024 16Bit fixed point arithmetics 2 FFTs at the same time by using

real and imaginary signal

Reconstruction afterwards needed

Algorithm Modules FFT FFT Subtraction In- / Output

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SLIDE 9

C(k)=A(k)W

k B(k)

D(k)=A( K )W

k B(k)

+ +

Wk A B C D

  • x

Noise-subtracting algorithm

Butterfly structure as fundamental cell

Algorithm Modules FFT FFT Subtraction In- / Output

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SLIDE 10

Noise-subtracting algorithm

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W0 W0 W2 W2 W3 W0 W2 W1 f(0) f(7) F(0) F(1) F(2) F(3) F(4) F(5) F(6) F(7)

Signal-flow Graph for 8 point FFT

Algorithm Modules FFT FFT Subtraction In- / Output

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SLIDE 11

Noise-subtracting algorithm

Sequential implementation 1Bit shiftdown after each step to

prevent overflow

RAM 1024 x 32Bit Controller (Finite state machine) Address generator Coefficient ROM

Algorithm Modules FFT FFT Subtraction In- / Output

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SLIDE 12

Noise-subtracting algorithm

ram_addr1

Controller Address Generator RAM Butterfly Processor

  • Coeff. ROM

rom_addr ram_addr2 twiddle write_en read_en

Data Bus

i

  • _

m

  • d

e fft_mode input_mode fft_done io_done bus_select

Data In Data Out

input_ready

  • utput_ready

1 10 10 32 32 32 32

FFT PROCESSOR

Block Diagram

Algorithm Modules FFT FFT Subtraction In- / Output

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SLIDE 13

Noise-subtracting algorithm

Delay estimation

  • Input:

512

  • FFT processing:

2*512*10

  • output:

512 Sum 11264 clock cycles

Algorithm Modules FFT FFT Subtraction In- / Output

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SLIDE 14

2000 4000 6000 8000 10000 12000 100 200 300 400 500 Verilog output abs(X1) 2000 4000 6000 8000 10000 12000 100 200 300 400 500 Matlab FFT (32 bit float) frequency abs(X2)

Noise-subtracting algorithm

Simulations

Algorithm Modules FFT FFT Subtraction In- / Output

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SLIDE 15

Noise-subtracting algorithm

Spectra reconstruction

1 2 (F(k)F(nk)) 1 2 (F(k)F(nk)) 1 2 (F(k)F(nk)) 1 2 (F(k)F(nk))

Re Im Re Im Re Im

Algorithm Modules FFT FFT Subtraction In- / Output

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SLIDE 16

Noise-subtracting algorithm

Error compared to 32bit floating point

2000 4000 6000 8000 10000 12000 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Absolute Error

Algorithm Modules FFT FFT Subtraction In- / Output

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SLIDE 17

Noise-subtracting algorithm

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

  • 1
  • 0.5

0.5 1 x 10

4

Time window weighted with hanning function (dumped from FFT memory) 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

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  • 0.5

0.5 1 x 10

4

) 500 2 sin( ) 1700 2 cos( t j t x ⋅ ⋅ + ⋅ ⋅ = π π

Error compared to 32bit floating point

Algorithm Modules FFT FFT Subtraction In- / Output

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SLIDE 18

1000 2000 3000 4000 5000 6000 1 2 3 4 x 10

5

Recontructed Spectra Matlab Verilog 1000 2000 3000 4000 5000 6000 1 2 3 4 x 10

5

frequency [Hz]

(absolute values plotted)

Noise-subtracting algorithm

Error compared to 32bit floating point

Algorithm Modules FFT FFT Subtraction In- / Output

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SLIDE 19

Noise-subtracting algorithm

16

Alpha Beta Sub Comp a

sel

b 1 if x>y, else 0 x Block diagram

Algorithm Modules FFT Subtraction Subtraction In- / Output

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SLIDE 20

Noise-subtracting algorithm

  • Inputs: two, 16 unsigned bits each

( A and B)

  • Multiplication: Alpha and Beta terms
  • Subtraction: ((original A)-(Alpha*B))
  • Comparators: (A > B) out =1, else out =0
  • Multiplexer:

(Inputs: Select, A*Beta, subtractor output)

Select = 1, final_out = x Select = 0, final_out = y

Algorithm Modules FFT Subtraction Subtraction In- / Output