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Flip-Flop One-bit Memory Something to Remember What I Remember D Q Remember Now! What I Remember Q Chapter 5 Edge-Triggered 1 3 CSc 314 T W Bennet Mississippi College CSc 314 T W Bennet Mississippi College State

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SLIDE 1

Chapter 5

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State

  • Combinational Elements: Adder
  • State Elements: Storage

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Flip-Flop

  • One-bit Memory

Something to Remember What I Remember What I Remember Remember Now!

Q Q’ D

  • Edge-Triggered

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Register

A collection of flip-flops

Q Q’ D Q Q’ D Q Q’ D Q Q’ D

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SLIDE 2

State Machines

  • Stored bit describes the state of the object.
  • A clock generates a regular pattern of voltage changes.
  • The state changes when the clock “ticks.”

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State changes when the clock rises.

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Counter: A State Machine

Oflow 1

Q Q’ D Q Q’ D Q Q’ D Q Q’ D

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Clocks and State Machines

  • At each tick, the machine does the “next” thing.
  • The faster the clock, the faster the machine.
  • The clock must be slow enough for changes to

propagate back to the registers during a clock cycle.

  • This is what those computer ads are talking about.

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SLIDE 3

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Datapath and Control

  • Datapath: Moving, storing, and creating data.
  • Control: Making each of those happen at right place and

time.

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Building the Datapath

  • Parts.
  • Sub-assemblies.
  • Complete datapath.

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SLIDE 4

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Datapath For Fetching

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Datapath For R-Type Instructions

Read reg 1 Read reg 2 Write reg sreg2 destreg

  • p

shft amt sreg1 funct 6 6 5 5 5 5 CSc 314 · T W Bennet · Mississippi College

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SLIDE 5

Datapath For Loading and Storing

Read Reg 1 Write register Read Reg 2 Others Loads

  • p

6 5 5 Rdest Rbase Offset 16 CSc 314 · T W Bennet · Mississippi College

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Datapath for Branching

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Datapath Combined

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Control

  • Signals the devices what they must do.
  • Interprets the instruction.
  • A large combinational circuit.

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SLIDE 6

Add Control Units

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ALU Controller

  • Inputs: Low six bits of the instruction (function code),

and two bits sent from the main controller.

sreg2 destreg

  • p

shft amt sreg1 funct 6 6 5 5 5 5

R

  • Outputs: ALU Function selection.

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ALU Control Signals

ALU Control Input ALU Function 0000 and 0001

  • r

0010 add 0110 subtract 0111 set on less than 1100 NOR

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Secondary Controller

From Main Func Output 00 XXXXXX 0010 X1 XXXXXX 0110 1X XX0000 0010 1X XX0010 0110 1X XX0100 0000 1X XX0101 0001 1X XX1010 0111 Determine what ALU needs to do based on the main controller’s direction and the function code from the instruction.

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SLIDE 7

Main Control

  • Input: High six bits of the instruction (op code).

sreg2 destreg

  • p

shft amt sreg1 funct 6 6 5 5 5 5

R

  • p

6 5 5

I

Rdest Rbase Offset 16

  • Outputs: RegDst, Branch, MemRead, MemtoReg,

AULOp, MemWrite, ALUSrc, RegWrite.

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Main Control: Output Signals

Mem- Instruction RegDst ALUSrc toReg RegWrite R-Format 1 1 lw 1 1 1 sw X 1 X beq X X Mem- Mem- ALU ALU Instruction Read Write Branch Op1 Op2 R-Format 1 lw 1 sw 1 beq 1 1

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Main Control: Input Signals

Op Code: First Six Instruction Bits Instruction Op5 Op4 Op3 Op2 Op1 Op0 R-Format lw 1 1 1 sw 1 1 1 1 beq 1

  • Just a large, combinational circuit.

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Single-Cycle Implementation

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SLIDE 8

Single-Cycle

Problems:

  • The cycle must be long enough for the longest

instruction.

  • Components must be duplicated, as the second ALU.

A Solution:

  • Shorter cycle.
  • Multiple cycles per instruction.
  • Different numbers of cycles for different instructions.

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Changes for Multi-Cycle

  • A single memory unit for both instructions and data.
  • A single ALU, rather than an ALU and two adders.
  • Add internal registers to hold the results of each cycle for

the next.

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High-Level View

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SLIDE 9

Full Multi-Cycle Implementation

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SLIDE 10

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SLIDE 11

Multi-Cycle Operation

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Control Logic

Compute the Outputs from the Inputs

  • Lots of gates.
  • ROM
  • Etc.

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SLIDE 12

An Alternative: Microcode

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Address Select Logic

01 11 10 00

ROM 1 ROM 2

Addr In Addr In Data Out Data Out

Next Address (State) Curr Address + 1 Op Code (From IR) Sequence Control (From microinstruction)

Microcontroller Address Select Logic

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Microinstructions

  • One large instruction for each state.
  • Specifies the signals to generate.
  • Specifies the next instruction.

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SLIDE 13

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Exceptions and Interrupts

Jump to the O/S upon certain events. Event Source MIPS Term I/O Device Request External Interrupt User Program Calls O/S (Syscall) Internal Exception Arithmetic Overflow Internal Exception Undefined Instruction Internal Exception Hardware Malfunction Either Either

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Types of Exceptions

  • Vectored: Jumps to different locations based on type of

exception or interrupt.

  • Cause Register: Store a code for the cause of the

exception in a special register, then jump to a standard place.

  • MIPS uses the later.

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SLIDE 14

MIPS Exception Registers

  • EPC: Holds the address of the offending instruction.
  • Cause: Holds a code for the cause of the exception.

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Exceptions

For the example implementation, we consider two exceptions

  • Undefined instruction: Code 0.
  • Arithmetic overflow: Code 32.

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Exception Datapath

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