[PPT] - PATMOS 2010 An On-Chip Flip-flop Characterization Circuit Andrea PowerPoint Presentation

SLIDE 1

PATMOS 2010 An On-Chip Flip-flop Characterization Circuit

Andrea Veggetti (ST Agrate) Abhishek Jain (ST Noida) Dennis Crippa (ST Agrate) Pier Luigi Rolandi (ST Agrate)

SLIDE 2

Agenda

Motivation
Flip-flop Characterization Parameters
Proposed Solution (Flip-flop Characterization

Circuit)

Modes of Operation
CAD Results
Silicon Results
Conclusions

2

SLIDE 3

Motivation

Flip-flops -> Vital Component in Sequential
Circuits. Their Performance determines the

performance of circuit.

To observe the Correlation between CAD

signoff and actual values on Silicon.

Accurate Measurements of pico-second order

delays can only be done by On-Chip methods.

With technology advancements flip-flops circuits

are getting more and more complex with more

features. Need to validate their performance on

Silicon.

3

SLIDE 4

Flip-flop Characterization Parameters

Timing Parameters

– Setup Time – Hold Time – Clock to Output Delay

4

Power Parameters

– Static Power

Under different configurations

– Dynamic Power

With Different Data Activity Rates

SLIDE 5

Proposed Solution

Single On-chip mesurement system for both timing and power

characterization.

Consists of optional digital Controller and Characterization circuit.
Characterization unit could be programmed to operate in different

configurations – Oscillator for Timing Characterization – Shift Register for Power Characterization.

Timing values are extracted from difference of period of oscillations of
scillator in different configurations.
Power characterization is done at dedicated power supply for DUT.

5

Flip-flop Characterization Circuit (FCC)

SLIDE 6

Proposed Solution (Contd.)

6

Data and Clock path could

programmed using muxes.

Multiple stages to be repeated

to have accurate mesurement and resolution.

Two different power domains

for accurate power mesurement.

– Default (for complete Circuit) – Vddff (for DUT)

Clock and Data Path Delay

units are based upon delay cells with very small delay difference of pico-seconds

rder.
Alternate stage of Basecell

consists of alternate polarity to minimize rise-fall error.

SLIDE 7

Oscillator Configuration Timing Parameter Characterization

7

SLIDE 8

Shifter Configuration Power Parameter Characterization

8

External Data and Clock applied to flip-flop.
Dedicated Power supply for flip-flop under test.
Dynamic Measurement:-
Power measurements are performed for different data activity rates.
Static Measurment:-
Power measurements are performed for different Data, Clock and

Output configuration.

Different Power Supply Domain vddff

SLIDE 9

CAD Results: Timing Parameters

9

50

50 100 150 200

80.00
60.00
40.00
20.00

0.00 20.00 40.00 60.00

TCP-Q (Measured) TCP-Q (Actual)

50

50 100 150 200

80.00
60.00
40.00
20.00

0.00 20.00 40.00 60.00

TCP-Q (Measured) TCP-Q (Actual)

20

30 80 130 180

50

50 100 150 200

TCP-Q (Measured) TCP-Q (Actual)

20

30 80 130 180

50

50 100 150 200

TCP-Q (Measured) TCP-Q (Actual)

Simulation Setup:-
CMOS 40nm Technology Node
Synopsys XA simulator
100 Stage Characterization

Circuit

DUT: Master Slave D Flip-flop

based upon C2MOS Tristate Latches

Simulation Corner:

TYP_1.0V_25C.

Timing Parameter

Characterization:

Hold Time: 5ps
Setup Time: 70ps
CLK to Q Delay: 132ps
Sources of Error:
8-10ps due to different path

delays of MUX

Clock-to-Delay(ps) Vs Clock-Data Path Delay(ps) for Hold Time Estimation Clock-to-Delay(ps) Vs Clock-Data Path Delay(ps) for Setup Time Estimation CP – D Delay CP – D Delay

SLIDE 10

CAD Results: Power Parameters

10

0.00E+00 1.00E-06 2.00E-06 3.00E-06 4.00E-06 5.00E-06 6.00E-06 7.00E-06 8.00E-06 9.00E-06 50% 33% 25% 20% 17% 14% 13% 11% 10%

DUT Power

0.00E+00 1.00E-06 2.00E-06 3.00E-06 4.00E-06 5.00E-06 6.00E-06 7.00E-06 8.00E-06 9.00E-06 50% 33% 25% 20% 17% 14% 13% 11% 10%

DUT Power

0.00E+00 2.00E-06 4.00E-06 6.00E-06 8.00E-06 1.00E-05 1.20E-05 1.40E-05 0.9V 1.0V 1.2V

DUT Power

0.00E+00 2.00E-06 4.00E-06 6.00E-06 8.00E-06 1.00E-05 1.20E-05 1.40E-05 0.9V 1.0V 1.2V

DUT Power

Dynamic Current in amps through hundred DUT stages Vs Data Activity Rate w.r.t. to Clock at 1V, 25C and 10MHz Clock Frequency Leakage Current in amps through hundred DUT stages Vs Applied Voltage at 150C

Power Measurements Performed On DUT power supply VDDFF

SLIDE 11

Silicon Results

11

40nm Mercury Testchip in SAMSUNG CMOS process.
100 stage Design implemented to measure Clock to Q delay.
DUT: Master Slave D Flip-flop based upon C2MOS Tristate Latches
2% misalignment between CAD and Silicon at nominal voltage range.
12% misalignment between CAD and Silicon at Lower Voltage.

CAD Vs Silicon Results for Clock-to-Q Delay (sec)

MERCURY_C40LP 3mm X 3mm Ultra Low Voltage IPs Fourtune Memory Cuts BISC for Access Time Characterization Fourtune ALLCELL structures Low Power Block 1 Low Power Block 2 Ring Oscillator Structures MERCURY_C40LP 3mm X 3mm Ultra Low Voltage IPs Fourtune Memory Cuts BISC for Access Time Characterization Fourtune ALLCELL structures Low Power Block 1 Low Power Block 2 Ring Oscillator Structures MERCURY_C40LP 3mm X 3mm Ultra Low Voltage IPs Fourtune Memory Cuts BISC for Access Time Characterization Fourtune ALLCELL structures Low Power Block 1 Low Power Block 2 Ring Oscillator Structures MERCURY_C40LP 3mm X 3mm Ultra Low Voltage IPs Fourtune Memory Cuts BISC for Access Time Characterization Fourtune ALLCELL structures Low Power Block 1 Low Power Block 2 Ring Oscillator Structures

0.00E+00 5.00E-11 1.00E-10 1.50E-10 2.00E-10 2.50E-10 3.00E-10 T=-40.00 V=0.90 T=-40.00 V=1.00 T=-40.00 V=1.10 T=25.00 V=0.90 T=25.00 V=1.00 T=25.00 V=1.10 T=125.00 V=0.90 T=125.00 V=1.00 T=125.00 V=1.10 CP-Q Rise Arc Silicon CP-Q Fall Arc Silicon CP-Q Rise Arc CAD CP-Q Fall Arc CAD 0.00E+00 5.00E-11 1.00E-10 1.50E-10 2.00E-10 2.50E-10 3.00E-10 T=-40.00 V=0.90 T=-40.00 V=1.00 T=-40.00 V=1.10 T=25.00 V=0.90 T=25.00 V=1.00 T=25.00 V=1.10 T=125.00 V=0.90 T=125.00 V=1.00 T=125.00 V=1.10 CP-Q Rise Arc Silicon CP-Q Fall Arc Silicon CP-Q Rise Arc CAD CP-Q Fall Arc CAD

Mercury_C40LP

SLIDE 12

Conclusions

12

Single system for complete characterization of flip-flop is presented.
The system gives high accuracy and high resolution.
Useful for SPICE model validation
Useful for Comparative Analysis of Different flip-flop structures.
CAD analyisis shown for complete system shows good results and

error under acceptable limits.

Sub-system to measure Clock to Q delay has been proven on

silicon.

Complete system to be validated on silicon.
System could be used for different flip-flop types.
System could be improved further to do characterization at different

load and slopes.