Flip-Flops Assume the an edge-triggered flip-flop FF implements a - - PowerPoint PPT Presentation

flip flops
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Flip-Flops Assume the an edge-triggered flip-flop FF implements a - - PowerPoint PPT Presentation

An edge-triggered flip-flop is not a combinational circuit. Claim: An edge-triggered flip-flop is not a combinational circuit.


slide-1
SLIDE 1

Flip-Flops

  • An edge-triggered flip-flop is not a combinational circuit.

Proof: Every combinational circuit implements a Boolean function. We show that an edge-triggered flip-flop is not an implementation

  • f any Boolean function.

Assume the an edge-triggered flip-flop FF implements a Boolean function f with propagation delay tpd(f ) . Claim: An edge-triggered flip-flop is not a combinational circuit.

  • f

t CLK

pd

  • 2
  • For CLK = 0 and D = 0, f(0,0) = Q = 1.

For CLK = 0 and D = 0, f(0,0) = Q = 0.

i

C

i

A

1

  • i

C

1

  • i

A

f t pd 1

CLK t D t Q

  • FF doesn’t implement any Boolean function.
  • FF is not a combinational circuit.

f t pd

FF

i

INV 2 FF’ t D t D

  • '

t Q' t Q

Overcoming non-empty intersection of Ci and Ai

cont hold

t t FF

  • :
  • :
  • INV

CONT INV

  • cont

hold j

t t INV CONT j i

  • 2

min

su su

t t

  • hold

hold

t t

  • INV

CONT i t t

cont cont

  • 2
  • INV

PD i t t

pd pd

  • 2
slide-2
SLIDE 2
  • MUX

PD t t

su su

  • MUX

CONT t t

hold hold

  • cont

cont

t t

  • pd

pd

t t

  • i

C

i

A

CLK t CE t D , t Q t DFF

CONT(MUX) PD(MUX)

Clock enabled edge-triggered flip-flop

MUX FF t D t CE CLK t Q

Definition: An edge-triggered flip-flop with a reset signal is defined as follows: . clock a and , signals Digital : Inputs CLK t RST t D

.

signal Digital : Output t Q

  • cont

i pd i i

t t t t t C t RST t D

  • 1

, every for then , segment critical the during stable are and If : ity Functional

  • 1

if if

i i i

t RST t RST t D t Q

An edge-triggered flip-flop with a reset signal

MUX FF t D t RST CLK t Q

Changing the flip-flop parameters (0)

FF t Q t D CLK

  • ,
  • FF

t FF t

hold su

G

  • G

t G t

cont pd

i

G A concatenation of i G gates:

  • G

t i G t

pd i pd

  • G

t i G t

cont i cont

  • Goal:

(1) Design an edge-triggered flip-flop FF’ with thold(FF)

  • 0.

(2) Design an edge-triggered flip-flop FF’’ with tsu(FF)

  • 0.

FF

i

G FF’ t D' t Q t Q

  • '

t D

CLK

  • G

t i FF t F F t

pd su su

  • G

t i FF t F F t

cont hold hold

  • FF

t F F t

cont cont

  • FF

t F F t

pd pd

  • G

t FF t i

cont hold

  • F

F thold

Changing the flip-flop parameters (1)

slide-3
SLIDE 3

Changing the flip-flop parameters (2)

  • G

t i FF t F F t

cont su su

  • G

t i FF t F F t

pd hold hold

  • G

t i FF t F F t

cont cont cont

  • G

t i FF t F F t

pd pd pd

  • CLK

CONT(Gi) PD(Gi) CONT(Gi) PD(Gi)

X

  • G

t FF t i

cont su

  • F

F tsu

FF

i

G FF’’

t Q t Q

  • t

D t D

  • CLK

X