First Results of 0.15 ! m CMOS SOI Pixel Detector SLAC Exp. Seminar, - - PowerPoint PPT Presentation

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First Results of 0.15 ! m CMOS SOI Pixel Detector SLAC Exp. Seminar, - - PowerPoint PPT Presentation

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Also presented at International Symposium on Detector Development, SLAC, Stanford Univ., April 3-6, 2006 First Results of 0.15 ! m CMOS SOI Pixel Detector SLAC Exp. Seminar, Apr. 4, 2006 Yasuo Arai (KEK) KEK Detector Technology Project :

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SLIDE 1

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 1

First Results of 0.15!m CMOS SOI Pixel Detector

SLAC Exp. Seminar, Apr. 4, 2006 Yasuo Arai (KEK) KEK Detector Technology Project : [SOIPIX Group]

  • Y. Arai!Y. Ikegami!H. Ushiroda!
  • Y. Unno!O. Tajima!T. Tsuboyama!
  • S. Terada!M. Hazumi!H. IkedaA!
  • K. HaraB!H. IshinoC!T. KawasakiD!

Gary VarnerE, Elena MartinE, Hiro TajimaF KEK!JAXAA!U. TsukubaB!TITC! Niigata U.D!U. HawaiiE, SLACF

Also presented at International Symposium on Detector Development, SLAC, Stanford Univ., April 3-6, 2006

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SLIDE 2

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 2

  • 1. Introduction

What is Silicon-On-Insulator?

  • 2. SOI Pixel Development at KEK
  • 3. Specific Issues on SOI Pixel

TCAD Simulation

  • 4. Test Results
  • 5. Summary

OUTLINE

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SLIDE 3

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 3

What is Silicon-On-Insulator?

Transistor 1!m

  • 1. Introduction

! A thin layer (50nm ~ 100!m) of

Si layered on SiO2

! Higher speed (up to 15%) and

Lower power (up to 20%) over Bulk CMOS.

OKI Electric Industry Co., Ltd.

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SLIDE 4

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 4

Feature of SOI-CMOS Devices

  • Full Dielectric Isolation : Latchup Free, Small Area
  • Low Junction Capacitance : High Speed, Low Power
  • Low Leakage, Low Vth Shift : High Temp. (~300 ºC) Application
  • High Soft Error Immunity : Rad-Hard application

(Ref. 'SOI Technology' by Jean-Pierre Colinge, Springer)

Bulk CMOS SOI CMOS

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SLIDE 5

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 5

PD vs. FD IBM PowerPC, AMD Athlon, Sony Cell … OKI Radio Controlled Wrist Watch (CASIO)

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SLIDE 6

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 6

SOI Wafer Fabrication"UNIBONDTM, SOITEC# CMOS (Low R) Sensor (High R)

microbubbles hydrophilic bonding ~500oC

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SLIDE 7

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 7

Previous Activity

Processed in

  • Lab. with ~3!m

technology. Ended at 2004?

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SLIDE 8

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 8

Last spring, New Detector R&D projects were called at KEK, and we proposed Development of SOI (Silicon-On-Insulator) Pixel Detector. Main members consist of Belle and ATLAS silicon detector group. Hybrid Pixel Detector (need many bump bondings) SOI Pixel Detector Monolithic Detector with Sensor(Hi-R) and Electronics(Low-R)

$%SOI Pixel Development at KEK

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SLIDE 9

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 9

Feature of Our SOI Pixel Detector

  • Using Commercial 0.15!m FD-SOI process (OKI Elec. Ind.).
  • SOI Wafer (SOITEC Hi-R, 150 mm")

Top Si : Cz, ~18 #-cm, p-type, 50 nm thick Buried Oxide: 200 nm thick Handle wafer: Cz!Hi-R >1k #-cm (No type assignment by supplier), 650 !m thick (thinned after process <350!m)

  • Multi Project Wafer (Masks are shared with other design)

+ additional process step.

  • Add only 3 mask layers to create sensor (p+, n+, and

contact to substrate).

  • Back side is plated with Al (200 nm).
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SLIDE 10

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 10

  • ’05. 6: OKI agreed on SOIPIX development with us.
  • ’05.10: 3 x 2"for p/n substrate) + 3 chips (total 9 chips) submitted.

"32x32 small pixel, 4x4 large pixel, Short strip, Tr TEG ...)

  • ’05.12: Test of contact fabrication.
  • ’06. 2: Test of p-n junction fabrication.
  • ’06.3 middle : Process ends.
  • ’06.3.30 Bare Chip Delivered.

(-> so the present results are very preliminary and limited)

Sensor (High Resistivity)

Al (2000A) p+ n+ BOX (Buried Oxide) 200nm 350um pixel pixel

Electronics

contact

TOP Si ~50nm

p-n junction

History

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SLIDE 11

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 11

Handling wafer p+ n+ Handling wafer Box SOI 650um

& After Gate stack formation ' Box Window photo lithography and etching ( Source/Drain Implantation followed by S/D annealing and Salicidation

Handling wafer Handling wafer

) 1st ILD (interlayer dielectrics) filling and CMP planarization

SOI Pixel Process step flow

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SLIDE 12

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 12

Handling wafer

* Contact etching

Handling wafer

+ Contact plug filling and 1st Metal formation

650um Al p+ n+ 250~350um

, 3 ~ 5Metal formation followed by Backside polishing and Al coating

Handling wafer

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SLIDE 13

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 13

n+ on p-- p+ on n-- Side View

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SLIDE 14

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 14

Small Pixel TEG

CMOS Active Pixel Sensor Type 20 !m x 20 !m 32 x 32 pixels

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SLIDE 15

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 15

8−12 DAC Analog sample (bussed) VIsrc Vbase buffer Analog Hold sample Row hit set baseline Collection electrode threshold Column Hit Sel Column VDD VDD Row enable Thresh

− + − +

IHXCP (Imaging Hard X-Ray Compton Polarimeter) TEG

Pixel Size 200 x 200 !m Pixel Array (Detector) Size 2.1 x 2.1 cm Noise <=10 e- Global Trigger Rate 500 Hz Single Pixel Rate 10? mili-Hz Trigger Threshold 0.5 keV Trigger Latency 1-2 !s Power 200 !W/pixel ADC precision 12 bits

U of Hawaii & SLAC

Target Specification

4 x 4 pixels

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SLIDE 16

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 16

  • n+, p+ implant

" Formed with Tr Source/Drain not to increase number of masks.

  • Thinning

" Wafer is thinned from 650um to 350um. Further thinning is possible.

  • Back Side process

" No implant on back side. Just add Al (2000 A) Plating.

  • Thermal Donor generation

Type of the high-R wafer may change by TD generation during process. " We prepared both p & n substrate designs.

  • Back Gate Effect to SOI Tr

Substrate works as back gate, so the voltage must be low under Tr. " All Tr are placed within Guard Ring, and body is tied to VDD/VSS.

  • 3. Specific Issues on SOI Pixel
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SLIDE 17

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 17

3D Process/Device Simulator ENEXSS

  • Developed by SELETE (Japan Consortium)

( http://www.selete.co.jp/ )

  • Full 3D simulation

gate d r a i n BOX SOI NMOS $ particle injection source

Useful to get # Field Map # Device Characteristics # Signal generated by particle, etc.

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SLIDE 18

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 18

Back Bias Simulation

  • ./0
  • ./1
  • ./2
  • ./3

. ./3 ./2 ./1 ./0 ./4

  • 2. -30
  • 5
  • 2

3. 36 7

VB (V) Threshold voltage (V) Backbias (V)

  • 20 -10 0 +10 +20

With |back bias| > 8V, NMOS or PMOS become always ON. Voltage of substrate under Tr must be kept low.

89:;: ENEXSS backbias supplied here NMOS handle wafer <=>

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SLIDE 19

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 19

4%Test Results MPW Wafer 6 inch"

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SLIDE 20

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 20

TEG Chip Layout

2.5 mm 20 !m 4 electrods/pixel Center of pixel is

  • pen for Light Test
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SLIDE 21

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 21

Contact & Sheet Resistance

[Sheet R] n+ : 33 #/square p+ : 136 #/square [Contact] (0.16x0.16um2) n+ : 87 # p+ : 218 #

Hi-R (> 1k #cm)

  • Std. wafer

(p+, ~13 #cm)

  • Std. wafer

(p+, ~13 #cm) Hi-R (> 1k #cm)

p+ contact n+ contact

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SLIDE 22

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 22

p-n junction I-V characteristics

p+(center) - n+ (guard) & n+(center) - p+(guard)

p+(center) - n+(guard) n+(center) - p+(guard)

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SLIDE 23

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 23

n+(center) – back is Ohmic " Substrate is n-type n+ - back

p+ - back n+ / p+ --- back I-V characteristics

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SLIDE 24

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 24

Substrate Resistivity [before process] No type assign, > 1 k#cm [after process] (4-points measurement) n-type, % ~700 #cm (->NB~6x1012 cm-3)

Very Preliminary!

10

  • 12

10

  • 11

10

  • 10

10

  • 9

10

  • 8

10

  • 7

10

  • 6

I[A] 60 50 40 30 20 10 Vdet[V]

I-V Characteristic 10um x 460um strip I<1nA @V=56 V Depletion ~ 100 !m ?

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SLIDE 25

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar) 25

5%Summary

  • We have started development of Monolithic SOI Pixel Detector.
  • The detector has sensor in high-resistive Si and CMOS circuit in low-

resistive Si.

  • We are using commercial (OKI 0.15 !m SOI) process with commercial

wafer (SOITEC Hi-R) with only adding 3 masks.

  • 3-D TCAD simulations for sensor/device study are being done with

ENEXSS?

  • Good substrate contact and p-n junction are confirmed with the first

run wafer.

  • We found type of handle wafer is ‘n’, and have enough resistivity.
  • 9 kinds of TEG chips are received at the end of March, and showing

promising results. Detailed tests will be done soon.

  • We would like to apply this technique to Super-B, SLHC, ILC and X-

ray detectors.