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Faster Adder Circuits for Inputs with Prescribed Arrival Times

Ulrich Brenner, Anna Hermann

Research Institute for Discrete Mathematics University of Bonn

Aussois, 10th January 2018

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Boolean Circuits

t4 t3 t2 t1 t0 t0 ∧

(t1 ∨ t2) ∨ (t3 ∧ t4)

• (t1 ∨ t2) ∧ (t3 ∧ t4)
• inputs

logic gates in B

• utputs

∧ ∨

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Boolean Circuits

t4 t3 t2 t1 t0 t0 ∧

(t1 ∨ t2) ∨ (t3 ∧ t4)

• (t1 ∨ t2) ∧ (t3 ∧ t4)
• (t1 ∨ t2) ∧ (t3 ∧ t4)
• inputs

logic gates in B

• utputs

∧ ∨

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Boolean Circuits

◮ A Boolean circuit is the implementation of a logical function

using logic gates of a basis B.

◮ Here, B := {∧, ∨}. t4 t3 t2 t1 t0 t0 ∧

(t1 ∨ t2) ∨ (t3 ∧ t4)

• (t1 ∨ t2) ∧ (t3 ∧ t4)
• (t1 ∨ t2) ∧ (t3 ∧ t4)
• inputs

logic gates in B

• utputs

∧ ∨

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Boolean Circuits

◮ A Boolean circuit is the implementation of a logical function

using logic gates of a basis B.

◮ Here, B := {∧, ∨}. t4 t3 t2 t1 t0 t0 ∧

(t1 ∨ t2) ∨ (t3 ∧ t4)

• (t1 ∨ t2) ∧ (t3 ∧ t4)
• (t1 ∨ t2) ∧ (t3 ∧ t4)
• inputs

logic gates in B

• utputs

∧ ∨

Boolean Circuit Optimization

Given a basis B and a Boolean function f : {0, 1}n → {0, 1}m, find a good circuit computing f over B.

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Depth of a Boolean Circuit

◮ Assume that input ti has arrival time 0. ◮ Assume that traversing a gate takes 1 time unit. ◮ The arrival time at gate g is a(g) = maxp∈δ−(g)

a(p) + 1.

Definition

The depth of a circuit C on inputs t0, . . . , tm−1 is the maximum arrival time of any node in C. Example: B = {∧, ∨}, f (t0, . . . , t4) = t0 ∧ (t1 ∨ (t2 ∧ (t3 ∨ t4)))

1 2 3 4 t0 t1 t2 t3 t4

Depth 4

t0 t1 t2 t3 t4 1 1 2 2 3

Depth 3

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Delay of a Boolean Circuit

◮ Assume that input ti has arrival time a(ti) ∈ N. ◮ Assume that traversing a gate takes 1 time unit. ◮ The arrival time at gate g is a(g) = maxp∈δ−(g)

a(p) + 1.

Definition

The delay of a circuit C on inputs t0, . . . , tm−1 with arrival times a(ti) ∈ N is the maximum arrival time of any node in C. Example: B = {∧, ∨}, f (t0, . . . , t4) = t0 ∧ (t1 ∨ (t2 ∧ (t3 ∨ t4)))

2 3 4 5 4 2 1 1 t0 t1 t2 t3 t4

Delay 5

4 2 1 1 t0 t1 t2 t3 t4 3 3 5 4 6

Delay 6

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Adder Circuits via And-Or-Path Circuits

Addition of two binary numbers (an−1 . . . a0) and (bn−1 . . . b0). Essential step: Computing the carry bits ci.

Example

1 1 1 1 + 1 1 1

1 1 1 1

1 1 1

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Adder Circuits via And-Or-Path Circuits

Addition of two binary numbers (an−1 . . . a0) and (bn−1 . . . b0). Essential step: Computing the carry bits ci.

Example

a0 + b0

c1

c1 = (a0 ∧ b0)

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Adder Circuits via And-Or-Path Circuits

Addition of two binary numbers (an−1 . . . a0) and (bn−1 . . . b0). Essential step: Computing the carry bits ci.

Example

. . . ai+1 ai . . . + . . . bi+1 bi . . .

. . . ci+1 ci . . .

c1 = (a0 ∧ b0) ci+1 = (ai ∧ bi)∨

• (ai ⊕ bi)∧ci
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Adder Circuits via And-Or-Path Circuits

Addition of two binary numbers (an−1 . . . a0) and (bn−1 . . . b0). Essential step: Computing the carry bits ci.

Example

. . . ai+1 ai . . . + . . . bi+1 bi . . .

. . . ci+1 ci . . .

c1 = (a0 ∧ b0) ci+1 = (ai ∧ bi)∨

• (ai ⊕ bi)∧ci
• = (ai ∧ bi)∨
• (ai ⊕ bi)∧
• (ai−1 ∧ bi−1)∨

(ai−1 ⊕ bi−1)∧ci−1

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Adder Circuits via And-Or-Path Circuits

Addition of two binary numbers (an−1 . . . a0) and (bn−1 . . . b0). Essential step: Computing the carry bits ci.

Example

. . . ai+1 ai . . . + . . . bi+1 bi . . .

. . . ci+1 ci . . .

c1 = (a0 ∧ b0) ci+1 = (ai ∧ bi)∨

• (ai ⊕ bi)∧ci
• = (ai ∧ bi)∨
• (ai ⊕ bi)∧
• (ai−1 ∧ bi−1)∨

(ai−1 ⊕ bi−1)∧ci−1

• =

t0 ∨

• t1

∧

• t2

∨

• t3

∧ . . .

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Adder Circuits via And-Or-Path Circuits

Addition of two binary numbers (an−1 . . . a0) and (bn−1 . . . b0). Essential step: Computing the carry bits ci.

Example

. . . ai+1 ai . . . + . . . bi+1 bi . . .

. . . ci+1 ci . . .

c1 = (a0 ∧ b0) ci+1 = (ai ∧ bi)∨

• (ai ⊕ bi)∧ci
• = (ai ∧ bi)∨
• (ai ⊕ bi)∧
• (ai−1 ∧ bi−1)∨

(ai−1 ⊕ bi−1)∧ci−1

• =

t0 ∨

• t1

∧

• t2

∨

• t3

∧ . . .

• ⇒ Fast circuits for these functions yield fast adder circuits.

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And-Or-Path Optimization

Definition

An And-Or-path on inputs t0, . . . , tm−1 is a function of type t0 ∧ (t1 ∨ (t2 ∧ (. . . tm−1))) or t0 ∨ (t1 ∧ (t2 ∨ (. . . tm−1))) .

t0 t1 t2 t3 t4

t0 ∧ (t1 ∨ (t2 ∧ (t3 ∨ t4)))

t0 t1 t2 t3 t4 t5

t0 ∨ (t1 ∧ (. . . ∨ t5))

Definition (Delay Optimization Problem for And-Or-Paths)

Let m > 0, inputs t0, . . . , tm−1 and arrival times a(ti) ∈ N for i = 0, . . . , m − 1 be given. Find a circuit realizing an And-Or- path on t0, . . . , tm−1 over the basis {∧, ∨} with minimum delay.

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Example for a Delay-Optimum And-Or-Path Circuit

2 3 2 3 3 2 2 4 1 3 4 5 6 7 8 9 10 11 12

Delay 12, number of gates 9

2 3 2 3 3 2 2 4 1 3 4 4 3 5 5 4 4 5 5 6 6 7

Delay 7, number of gates 12

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Known Results for Depth Optimization

Lower bound:

◮ Commentz-Walter [1979]: log2 m + Ω(log2 log2 m)

Upper bound:

◮ Grinchuk [2009]: log2 m + log2 log2 m + 3

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Lower Bound on Circuit Depth

1 1 1 1 1 2 2 3 4

Observation

Any circuit containing only 2-input gates with n inputs has depth at least ⌈log2 n⌉.

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Lower Bound on Circuit Delay

1 1 1 2 2 3 4

◮ Consider any circuit on inputs ti with arrival times a(ti).

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Lower Bound on Circuit Delay

1 1 1 2 a := 2 3 4

◮ Consider any input ti with arrival time a := a(ti) > 0. ◮ Replace ti by a full binary tree with depth a.

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Lower Bound on Circuit Delay

1 1 1 1 1 a := 2 2 3 4

◮ Consider any input ti with arrival time a := a(ti) > 0. ◮ Replace ti by a full binary tree with depth a. ◮ The tree has 2a inputs. ◮ This does not change the delay of the circuit.

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Lower Bound on Circuit Delay

1 1 1 1 1 2 2 3 4

◮ Iterating yields a circuit with W (t) := i 2a(ti) inputs.

Observation

Any circuit containing only 2-input gates on inputs t0, . . . , tm−1 with arrival times a(ti) has delay at least ⌈log2 W (t)⌉.

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Known Results for Delay Optimization

Let W := m

i=0 2a(ti) .

Lower bound:

◮ Huffman [1952] (Binary tree): ⌈log2 W ⌉

Upper bounds:

◮ Rautenbach et al. [2006] / Held, Spirkl [2017]:

1.441 log2 W + 2.673

◮ Spirkl [2014]: ⌈log2 W ⌉ + 2

2 log2 m + 6

◮ Here: log2 W + log2 log2 m + log2 log2 log2 m + 5

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Characterization of And-Or-Paths via Truth Assignments

t0 t1 t2 t3 t4 t7

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Characterization of And-Or-Paths via Truth Assignments

t0 t0 t1 t2 t2 t3 t4 t4 t7 t7

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Characterization of And-Or-Paths via Truth Assignments

t0 t1 t1 t2 t3 t3 t4 t4 t7

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Characterization of And-Or-Paths via Truth Assignments

t0 t1 t1 t2 t3 t3 t4 t4 t7

Observation

The output is true ⇐ ⇒ There is an input tk of an Or gate s.t.

◮ tk generates a true signal and ◮ each And gate after tk propagates the true signal.

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Well-Known Recursion Strategy

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t′ t′′

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Well-Known Recursion Strategy

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t′ t′′

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t′ t′′ 11 / 14

Well-Known Recursion Strategy

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t′ t′′

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t′ t′′ 11 / 14

Our Proof Strategy

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t′ t′′

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t′ t′′

Theorem (Brenner, H.)

Fix a delay bound d. Given inputs t with weight W (t) ≤

2d−1 d log2(d),

we can compute a circuit for an And-Or-path on t with delay d. Proof idea: Induction on d, extending Grinchuk’s proof [2009].

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Critical Part of the Proof

Inductive step

For inputs t with weight W (t) ≤

2d (d+1) log2(d+1)

, we can compute a circuit for an And-Or-path on t with delay d + 1. Proof idea:

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t′ t′′

large d d + 1 ?

Inductive step.

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Solution: Strengthen the Induction Hypothesis

Inductive step

For inputs t with weight W (t) ≤

2d (d+1) log2(d+1)+ d d+1Λt, we can

compute a circuit for an And-Or-path on t with delay d + 1. Proof idea:

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t′ t′′

large d d + 1 ?

Inductive step.

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Proof of Delay Bound

Step 1: Fix a delay bound d. For any inputs t with weight W (t) ≤ 2d−1 d log2(d) , we can compute a circuit for an And-Or-path on t with delay d. Step 2: Given inputs t and arrival times a(ti), we can compute a circuit for an And-Or-path on t with delay d ≤ log2 W (t) + log2 log2 W (t) + log2 log2 log2 W (t) + 5 . Step 3: Given inputs t and arrival times a(ti), we can compute a circuit for an And-Or-path on t with delay d ≤ log2 W (t) + log2 log2 m + log2 log2 log2 m + 5 .

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Proof of Delay Bound

Step 1: Fix a delay bound d. For any inputs t with weight W (t) ≤ 2d−1 d log2(d) , we can compute a circuit for an And-Or-path on t with delay d. Step 2: Given inputs t and arrival times a(ti), we can compute a circuit for an And-Or-path on t with delay d ≤ log2 W (t) + log2 log2 W (t) + log2 log2 log2 W (t) + 5 . Step 3: Given inputs t and arrival times a(ti), we can compute a circuit for an And-Or-path on t with delay d ≤ log2 W (t) + log2 log2 m + log2 log2 log2 m + 5 .

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Proof of Delay Bound

Step 1: Fix a delay bound d. For any inputs t with weight W (t) ≤ 2d−1 d log2(d) , we can compute a circuit for an And-Or-path on t with delay d. Step 2: Given inputs t and arrival times a(ti), we can compute a circuit for an And-Or-path on t with delay d ≤ log2 W (t) + log2 log2 W (t) + log2 log2 log2 W (t) + 5 . Step 3: Given inputs t and arrival times a(ti), we can compute a circuit for an And-Or-path on t with delay d ≤ log2 W (t) + log2 log2 m + log2 log2 log2 m + 5 .

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Thank you for listening!

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Practical Relevance

◮ The size of our circuit is at most 18m log2 m log2 log2 m. ◮ The maximum fanout of our circuit is at most

log2 m + log2 log2 m + log2 log2 log2 m + 4.1.

◮ Our algorithm has running time O(m2 log2 m). ◮ A dynamic program trying out all recursion steps has the same

delay guaranty and is successfully used on practical instances.

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