Fabrication of ATLAS pixel detector prototypes at IRST M. - - PowerPoint PPT Presentation

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

Fabrication of ATLAS pixel detector prototypes at IRST

• M. Boscardin, G.-F. Dalla Betta, P. Gregori, M. Zen, N. Zorzi

Centro per la Ricerca Scientifica e Tecnologica (ITC-irst), Località Pantè di Povo, 38050 Trento, Italy

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

Outline

• Introduction
• Description of the fabrication technology
• Fabrication of 1st and 2nd prototypes:

experimental results and problems

• Conclusions

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin
• In the last few years, IRST has been involved in the development
• f silicon microstrip detector technologies within an R&D project

supported by INFN.

• Starting from fall 1998, we have fabricated silicon pixel detectors
• riented to the ATLAS experiment (prototypes 1 and 2).
• We present the main processing issues and report some selected

results from the electrical characterization of detectors and test structures carried out before detector delivery.

Introduction

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

n-on-n pixel detector isolation with p-spray (or moderated p-spray) IRST microstrip technology p-stop BIAS dot

• verlap n+-region and p+-region
• verlap contact hole and n+- region

Process/Layout Constraints

develop a new process IRST microstrip tech. no overlap between n&p regions PROCESS LAYOUT RULES

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

initial oxide growth (200nm) p-spray implantation B 4.5E12 70KeV define moderated p-spray moderated p-spray implantation B 4.5E12 70KeV TEOS deposition (800nm) resist termal oxide TEOS

Process Flow (1/3)

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

define p+ region implant oxide growth (40nm) p+ implant (B 5E14 70KeV) define n+ region p+ drive-in (900°C in dryO2) n+ implant (P 5E15 120KeV) n+ drive-in (975°C in dryO2) TEOS deposition (300nm) low temperature annealing

Process Flow (2/3)

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

define and open contact holes (n&p side) metal deposition (1µm Al 1%Si) 1st LTO deposition (500nm) define metal (n-side) etch LTO and metal 2nd LTO deposition (500nm) define metal (p-side) etch LTO and metal 3rdLTO deposition (500nm) define and open passivation (n&p side) sintering

2nd LTO 1st LTO 3rd LTO

Process Flow (3/3)

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

moderated p-spray two separate implantations p-spray = blank + moderated p-spray = p-stop like p+ and n+ region implantation through a screen oxide using a thick oxide layer as implant mask low temperature annealing increase gettering efficiency metal and passivation LTO oxide to protect metal layer

Detector Fabrication: critical steps

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

Test Structures diode 4mm2 Ileak ≅ ≅ ≅ ≅ 300pA @ full depletion gated diode s0 ≅ ≅ ≅ ≅= = = =30 cm/sec IV curves of multiguard diode (area 2.2mm2)

Prototype 1: Experimental results

1.0E-11 1.0E-10 1.0E-09 1.0E-08 1.0E-07 200 400 600 800 Bias Voltage [V] Leakage Current [A] diode guard-ring

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

Vbk at low voltage (about 20V) probably due to a misalignement between contact and n-diff region Iback, Ip-spray with p-spray @ V=0 I back with p-spray floating

I p-spray I back I back

Prototype 1: Experimental results

1.0E-09 1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 20 40 60 80 Bias Voltage [V] Single Chip Current [A] 5 10 15 20 25 30 35 20 40 60 80 100 120 140 160 180 200 Breakdown Voltage [V] Number of Single Chip [%]

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

leakage current

• n single chip (ST SMD)

Ileak ≅ ≅ ≅ ≅ 7.5nA @ 50V layout

• verlap between contact

and n+ region = 2,5 µm To increase the radiation hardeness of detectors, wafers have been oxygen enriched via a dedicated process step (24h

• xidation process at 1150°C).

Prototype 2: Experimental results

LAD SMD NOD

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

ST SMD ST LAD

Single Chip: IV curves

1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 50 100 150 200 Bias Voltage [V] Leakage Current [A] 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 50 100 150 200 Bias Voltage [V] Leakage Current [A]

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

Single Chip: VBK & Ileak distributions

Breakdown of ST NOD < 140V Average Leakage Current @ 100V of ST SMD & LAD about 30 nA

5 10 15 20 25 30 60 90 120 150 180 210 240 270 1000 Leakage Current @ 100V [nA] Number of Single Chips [%] ST LAD ST SMD 10 20 30 40 50 60 70 20 40 60 80 100 120 140 160 180 200 Breakdown Voltage [V] Number of Single Chips [%] ST LAD ST NOD ST SMD

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

SMD LAD

Tiles: IV curves

1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 25 50 75 100 125 150 175 200 Bias Voltage [V] Leakage Current [A]

1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 25 50 75 100 125 150 175 200 Bias Voltage [V] Leakage Current [A]

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin

Tiles: Breakdown Voltage Distributions

Tiles with a VBK >150V NOD SMD 8 LAD 4 Tiles with a VBK = 20V NOD 10 SMD 7 LAD 15

10 20 30 40 50 60 20 40 60 80 100 120 140 160 180 200 Breakdown Voltage [V] Number of detectors [%] NOD SMD LAD

June 5 - 8, 2000 Pixel 2000, Genova

• M. Boscardin
• We have processed some prototype batches of silicon pixel

detector oriented to the ATLAS experiment.

• To this purpose, a dedicated technology has been developed.
• The electrical characterization of single chips and related test

structures have evidenced that IRST technology is potentially adequate for the fabrication of these detectors.

• However, results from tiles measurements have shown that the

number of process-related defects should be decreased in order to fulfill the detector specifications (in particular in terms of breakdown voltage) with a satisfactory fabrication yield.

Conclusions