Study of I ndium bumps f or the Study of I ndium bumps f or the - PowerPoint PPT Presentation

Study of I ndium bumps f or the Study of I ndium bumps f or the ATLAS pixel detector ATLAS pixel detector June, 7th 2000, Pixel2000, Genova, I taly G. Gagliardi, C.Gemme, P. Netchaeva, L. Rossi, E. Ruscino, F. Vernocchi University and I NFN of Genova, I taly A. M. Fiorello, M. Varasi Alenia Marconi Systems – Rome, I taly M. Gilchriese LNBL, USA On behalf of the ATLAS Pixel Collaboration 1 C. Gemme, University and I NFN, Genova

Outline Outline � I ntroduction � AleniaMarconiSystem (AMS) bump- bonding technique � Results: � Mechanical properties � Electrical Resistance � Yield of Electrical def ects � Conclusions 2 C. Gemme, University and I NFN, Genova

Modules layout Modules layout Bumps are at the same time the electrical and mechanical connection between sensor and electronics in a module MCC Flex- hybrid sensor bumps FEs Stave (C- C) Requirements: pitch: 50 µ µ m µ µ density: 5000 contacts/ cm 2 bumps/ module: ~50000 bumps/ ATLAS: ~10 8 The bump- bonding technology is used to join the f ront- end readout I Cs to the silicon sensor substrate: * bump deposition * f lip- chip assembly 3 C. Gemme, University and I NFN, Genova

AMS bump deposition AMS bump deposition � More details during this Waf er cleaning evening round table Photolitography � I ndium Bumps are deposited both on electronics and on silicon sensor waf ers through Plasma activation metal evaporation � Bump thickness: Evaporated 6. 8 ± ± 0. 2 µ µ m ± ± µ µ I ndium � Thickness unif ormity: ± ± ± 0. 3 µ ± µ m (6’’ waf er) µ µ � Fault rate (by optical inspection): Wet lif t of f (2. 0 ± ± ± ± 0. 6) 10 - 5 process 4 C. Gemme, University and I NFN, Genova

Flip- chipping Assembly Flip- chipping Assembly � Flip- chip is the process of mounting the integrated circuit die onto the silicon sensor substrate. � Bumps previously deposited on both the silicon sensor and the I C die are accurately aligned and then joined under pressure (FC6 Karl Suss Bonder). � Pressure, temperature and time are critical parameters to determine a good result of the f lip- chip. 5 C. Gemme, University and I NFN, Genova

AMS Flip- chip AMS Flip- chip � The choice of f lip- chip parameters is perf ormed with glass substrates to better investigate ef f ects on bumps 100°C/35N/40s 100°C/30N/40s 90°C/25N/42s 6 C. Gemme, University and I NFN, Genova

AMS Flip- chip AMS Flip- chip � Selected parameters: � Force: 25 N (per FE chip) � Substrate Temperature: 90 0 C � Chip Temperature: 90 0 C � Time: 42 sec � Bumps height : ~8 µ µ µ µ m (7 µ µ µ m + 7 µ µ µ µ µ m bumps pressed together) � Bump diameter: ~20 µ µ m µ µ � Tensile strength: ~0. 1 g/ bumps i. e. ~3 N/ FE � Check Flip- chip planarity 7 C. Gemme, University and I NFN, Genova

Test of f lip- chip planarity Test of f lip- chip planarity � To check the planarity in the f lip- chip process, the f lip- chip machine is tuned using bonded glass substrates and checks are done at the f our corners of the chip 8 C. Gemme, University and I NFN, Genova

Test of f lip- chip planarity Test of f lip- chip planarity T = 90 0 C F = 25 N t = 42 s As unif ormity of the bumps at the corner of the chip is verif ied, planarity obtained with the f lip- chip machine is good 9 C. Gemme, University and I NFN, Genova

Mechanical Stresses on bumps in real conditions… Bumps will be mechanically Bumps will be mechanically stressed during thermal cycles stressed during thermal cycles due to dif f erent CTEs CTEs of the of the due to dif f erent materials they bond (detector materials they bond (detector build at room T but operating at build at room T but operating at 0 C) T below 0 0 C) T below 0 Dummy module to simulate stress: Dummy module to simulate stress: µ m thick glass with µ µ µ 300 µ µ µ µ � Tile = Tile = 300 m thick glass with � Measurement I n bumps by AMS. I n bumps by AMS. points µ µ m thick FE chips µ µ 550 µ µ µ µ � C Ch hips = ips = 550 m thick FE chips � with I n bumps by AMS. with I n bumps by AMS. Flip- chip in Genoa I NFN lab. in Genoa I NFN lab. � Flip- chip � � Glue Glue between electronics and between electronics and � stave = cyanoacrylate, rigid stave = glue glue to enhance stresses to enhance stresses Carbon- carbon 10 C. Gemme, University and I NFN, Genova

Mechanical properties Mechanical properties � Bumps displacement measured with microscope at Bumps displacement measured with microscope at � edge of tile. edge of tile. � Measurements at - 10C, +20C and +40C, T Measurements at - 10C, +20C and +40C, T � measured with I R thermometer. measured with I R thermometer. � A dozen of cycles [- 20C, +20C], measured af ter A dozen of cycles [- 20C, +20C], measured af ter � each cycle in some cases rising to +40C (90% of each cycle in some cases rising to +40C (90% of time at - 20C, i. e. under stress). time at - 20C, i. e. under stress). � Periodically checked bump connectivity by measuring Periodically checked bump connectivity by measuring � the bump gap with microscope f ocus: this was the bump gap with microscope f ocus: constant af ter each cycle and equal to 8 ± 1 µ µ µ µ m (typically ~30 µ µ µ m when bump is disconnected). µ 11 C. Gemme, University and I NFN, Genova

= = = = Lef t edge (low side) Lef t edge (low side) � The red line represents a f ixed 50 µ µ µ m µ position on the chip. - 10 0 C � Max displacement measured is ~7. 5 µ µ m (f or ∆ µ µ ∆ ∆ = ∆ = T = 50 0 C) � No problem with bump connectivity � Due to dif f erent CTE between this glass and silicon, we expect f or ∆ ∆ = ∆ ∆ = T = 30 0 C a displacement of ~3 µ µ µ µ m 20 0 C 40 0 C 12 C. Gemme, University and I NFN, Genova

AMS bumping results: electrical measurements AMS bumping results: electrical measurements � Bump connection resistance must be small not to signif icantly contribute to the f ront- end noise. � I t is well known that I n develops an oxide layer once taken out of the vacuum tank where the bump deposition is done. I n 2 O 3 is an insulator. � I t is desirable that the oxide layer break automatically when the bias is applied to the electronics. 13 C. Gemme, University and I NFN, Genova

= = Constant voltage Constant voltage � Resistance of the bumps with a digital ohm- meter f or some bumps, bef ore and af ter applying 3V � Only 10% of the bumps have initially an oxide layer � The oxide resistance is quite low (~500K Ω Ω ) Ω Ω � Once the oxide is broken the bump resistance is unif ormly low (~10 Ω Ω Ω ) => ~2 Ω Ω Ω Ω Ω = = af ter subtracting the probe needles resistance 14 C. Gemme, University and I NFN, Genova

= = Resistance measurements notes Resistance measurements notes � AMS I n oxide is thin (low resistance O(500K Ω Ω Ω Ω ) = = and already broken in ~90% of the cases. Breaking the residual oxide requires low voltages (O(50mV)) f or some minutes. � The bump resistance af ter oxide breaking is low enough (O(2 Ω Ω Ω Ω )) to allow proper operation of the FE electronics. � The bump resistance af ter oxide breaking is stable in time and af ter thermal cycles. 15 C. Gemme, University and I NFN, Genova

How bumps work with real detector and real How bumps work with real detector and real electronics: electronics: Modules and single chips with AMS bumps Modules and single chips with AMS bumps � Dif f erent type of devices produced: single chips, modules, single chip and modules with thinned electronics. � A total of about 100K channels investigated � I t is possible to investigate def ects due to the bump bonding: � Merged pixels: neighbouring bumps are connected � Missing pixels: no contact between sensor and electronics � X- ray analysis of some f lip- chipped devices of f ers the opportunity to correlate the bump def ects and the electrical behaviours of the pixels. 16 C. Gemme, University and I NFN, Genova

Pixel test Pixel test � I n our lab we can test each pixel by a digital injection, an analogue scan and with a radioactive source. Block diagram f or one pixel Analogue injection Digital injection Sensor Bump pad Preamplif ier Discriminator Masking 17 C. Gemme, University and I NFN, Genova

Test procedure Test procedure � Digital injection to test the digital part of the pixel electronics and the overall FE electronics. � Analogue scan to measure threshold and noise f or each pixel. Scan voltage(mV) noise(e - ) Threshold(e - ) 18 C. Gemme, University and I NFN, Genova

Test procedure: looking f or merged bumps Test procedure: looking f or merged bumps � From the analogue scan we identif y: Noise plot � Good electronics channels � Bad pixels (never responding to the injection): Merged pixel � High t hreshold � Non-working preamplif ier � Merged bumps: charge goes in a neighbouring pixel which result s noisier as it sees more sensit ive area Threshold � With an automatic program suspected merged pixels can be identif ied Noise 19 C. Gemme, University and I NFN, Genova