Early Prediction of Product Performance and Yield Via Technology - - PowerPoint PPT Presentation

Early Prediction of Product Performance and Yield Via Technology Benchmark

Choongyeun Cho1, Daeik D. Kim1, Jonghae Kim2, Daihyun Lim1, Sangyeun Cho3

1IBM, 2Qualcomm, 3U. Pittsburgh

2

Background

• Process variation as grave concern:

– Limits IC product performance and yield – Difficult to model / predict before tape-out

• Product circuit is tested and qualified

usually after BEOL process is complete

– Test for final product is often expensive in terms of cost, time and resource

3

Background

• Typical schedule for CMOS technology

development and testing:

BEOL FEOL

PC BOX Si 1X 2X 4X 8X SiO2 CA

Far- BEOL t0 t1 t2 t5 tN-1 tN Substrate FEOL Inline benchmark test Si CMOS Technology Processing Wafer-level test Chip-level test Function block test Circuit test t7

Wk 0 Wk 10 Wk 12 Wk 15 Wk 17 Wk 20 Wk 24

• 10

FEOL t0 Inline 12 M1 t1 Block 15 M5 t5 Wafer 20 Mtop tN-1 Chip 24 C4 tN Test Time (Week) Level Step

• 10

FEOL t0 Inline 12 M1 t1 Block 15 M5 t5 Wafer 20 Mtop tN-1 Chip 24 C4 tN Test Time (Week) Level Step

4

Motivation

• Use existing M1 data to predict

product performance / yield

– Device characterization is available early in manufacturing, typically at M1 level – M1 test data, if prudently selected, carries relevant information to reliably predict product performance and yield

5

Motivation

• Will reduce test cost and time for

product circuit performance / yield

FEOL+M1 Process FEOL+M1 Process BEOL Process BEOL Process

Model Time Bench- Mark Bench- Mark Tests Tests Yield Circuit Yield Yield Circuit Circuit

This work

FEOL+M1 Process FEOL+M1 Process BEOL Process BEOL Process

Model Time Bench- Mark Bench- Mark Tests Tests Yield Circuit Yield Yield Circuit Circuit

This work This work

FEOL+M1 Process FEOL+M1 Process BEOL Process BEOL Process

Model Model Time Bench- Mark Bench- Mark Calibration Tests Tests Yield Yield Circuit Circuit

Conventional

FEOL+M1 Process FEOL+M1 Process BEOL Process BEOL Process

Model Model Time Bench- Mark Bench- Mark Calibration Tests Tests Yield Yield Circuit Circuit

Conventional Conventional

Conventional This Work

6

Methodology

Nonlinear estimator

Product Parametric

m n p 1

Predictor

M1 Data Feature extraction Data filtering Nonlinear estimator

Product Parametric

m n p 1

Predictor

M1 Data Feature extraction Data filtering

Well-chosen M1 data captures key process variation mechanisms (Vth, Tox, Lpoly, etc) Remove outlier and statistically unimportant parameters Use projected principal component to extract features while preserving most information relevant circuit parameters Neural net is employed to estimate product performance or yield

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Training and Testing

Predictor Training

M1 data

Product parameter Predictor Training Predictor Training

M1 data

Product parameter Predictor Training

Estimated Product Parameter Product Parameter

Error

Predictor Testing Predictor Testing

M1 data

• +

Estimated Product Parameter Product Parameter

Error

Predictor Testing Predictor Testing

M1 data

• +

65nm SOI technology used for validation (12 wafers)

8

Experiment: 65nm SOI

• M1 data set as an input:
• 10 wafers used for training, 2 wafers used for testing

2,856 222 398 248 1,988 # of parameters (before screening) 159 SRAM 108 Capacitance 1,109 Total 83 RO 759 FET # of parameters (after screening) M1 test structure category

9

Validation Circuit

• Two product circuits

chosen for validation

• f proposed method
• 1. Freq. divider as PLL

component: self-osc

• freq. is estimated
• 2. Ring oscillator as

logic product: gate delay of 101-stage inverter-based RO is predicted

MIBS MIBS

31mm 25mm

EN EN

DFF DFF

PLL Logic

RF divider Ring oscillator CML Inverter

MIBS MIBS

31mm 25mm

EN EN

DFF DFF

PLL Logic

RF divider Ring oscillator CML Inverter

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Prediction Results

Ring Osc Freq divider 13.1%

• 25.6%

Yield 5.1% 0.28mA (11.1%) 2.5mA IA,RO 3.5% 0.37ps (8.7%) 4.3ps Delay 17.7% 10.0% 4.6% Neural Net %err 27.5% 24.0mA 34.6GHz Mean

• 3.6mA (15.1%)

2.9GHz (8.3%) Std dev Yield Idd Self-osc freq. Estimated parameter

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Prediction Results

Self-osc Freq Idd Yield Delay I_A Yield 5 10 15 20 25

Prediction error (%)

Linear fit Quadratic fit Neural network

• Neural net is slightly more accurate than linear

estimator

• Error comes mainly from: (1) BEOL variation and (2)

Intra-die variation

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Prediction Robustness

• To evaluate the estimation

robustness, training and testing data sets are divided to slow and fast, and prediction was performed

• The prediction error does

not strongly depend on any particular combination of training / testing data sets

• The proposed method is

robust even when wafer variation is significant

4.9% Fast Fast Slow Fast Slow Testing set Fast Slow Slow Training set 5.5% 5.6% 4.5% %err

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Feedback to Design / Tech

• Mapping from M1 measurement to

product performance metric:

– For technology, it reveals what device characteristics are most sensitive to product, and to what degree – Designer can make educated trade-off between design parameters – E.g. RO gate delay is related to tech parameters:

th

• ff
• n

V I I 765 . 817 . + + ∝ τ

(each parameter normalized)

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Conclusion

• Proposed an efficient statistical

method to predict circuit performance and yield solely based on technology benchmark data available at M1

– <5% error for estimating mmWave freq. divider performance – <4% error for RO gate delay

• This method significantly cuts time

and cost of final product test