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Digital System Design Lecture 12: Altera-Xilinx SOPC Amir Masoud - - PowerPoint PPT Presentation
Digital System Design Lecture 12: Altera-Xilinx SOPC Amir Masoud - - PowerPoint PPT Presentation
Digital System Design Lecture 12: Altera-Xilinx SOPC Amir Masoud Gharehbaghi amgh@mehr.sharif.edu Altera Nios-II CPU Architecture 32-bit general-purpose processor (instruction, data, address) 32 general-purpose registers 32
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Nios-II Family
Three versions
Fast (Nios-II/ f): Optimized for
maximum performance
Economy (Nios-II/ e): Optimized for
minimum logic usage
Standard (Nios-II/ s): Offers a balance
between performance and size
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Nios-II Family Summary
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- Pipeline stages
512 B - 64 KB 512 B - 64 KB
- Instruction Cache
512 B - 64 KB
- Data Cache
256 256 256 Custom Instructions Dynamic Static
- Branch prediction
135 MHz 135 MHz 150 MHz Frequency (max) < 1800 < 1300 < 600 Size (LEs) Nios-II/ f Nios-II/ s Nios-II/ e Feature
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Nios-II Device Support
Stratix-II:
Highest-performance, highest-density
Stratix:
High-performance, high-density
Stratix GX:
High-performance architecture with high-speed
serial transceivers
Cyclone-II:
Lowest-cost FPGA
Cyclone:
Low-cost ASIC replacement
HardCopy-II & HardCopy:
The industry’s first structured ASIC that offers a
comprehensive alternative to traditional ASICs
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Additional IP Megafunctions
PCI Controller 32 & 64 bits UART Floating Point Arithmetic Unit DMA Controller Ethernet MAC (1000/ 100/ 10 Mbps) USB Controller Serial ATA Controller …
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Development Tools
Hardware Generation:
SOPC Builder Quartus-II
Software Development:
Nios-II IDE
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Cyclone-II Block Diagram
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Cyclone-II Feature Summary
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Stratix-II Block Diagram
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Stratix-II Feature Summary
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Xilinx Virtex-4 Family
Three Families:
Virtex-4 LX:
High-performance logic applications
solution
Virtex-4 FX:
High-performance, full-featured solution
for embedded platform applications
Virtex-4 SX:
High-performance solution for Digital
Signal Processing (DSP) applications
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Virtex-4 Family Overview
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Virtex-4 FX Feature Overview
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RocketIO Multi Gigabit Tranceiver
Full-duplex serial transceiver (MGT)
capable of 622 Mb/ s to 10+ Gb/ s baud rates
CRC generation and checking Receiver signal detect and loss of
signal indicator
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PowerPC 405 RISC Core
32-bit RISC Processor Up to 450 MHz operation Five-stage data path pipeline 16 KB instruction cache 16 KB data cache Auxiliary Processor Unit (APU)
Interface
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Tri-mode Ethernet Media Access Controller (MAC)
IEEE 802.3 compliant Operates at 10, 100, and 1,000
Mb/ s
Supports tri-mode auto-detect Half or Full Duplex Flexible, user-configurable host
interface
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Xilinx Design Tools
Logic Design
ISE
Embedded Design
EDK ChipScope Pro System Generator (DSP)
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