Preface There are more slides here than will be used in lectures. - - PDF document

Preface

There are more slides here than will be used in

• lectures. The slides not covered will be listed
• n the website.

At least 10 minutes or so of each lecture will be devoted to example material, including pre- vious exam questions, for which there are no slides in this handout.

1

Books related to the course

Suggested books include: W.Ditch. ‘Microelectronic Systems, A practi- cal approach.’ Edward Arnold. The final chap- ters with details of the Z80 and 6502 are not relevant to this course. Floyd. ‘Digital Fundamentals’ Prentice Hall International. T.J. Stoneham. ‘Digital Logic Techniques’ Chapman and Hall. This is a basic book and relates more to the previous course on Digital Electronics. Randy H Katz. ‘Contemporary logic design.’

2

A Broadside Register

Broadside register

N N Clock Q D D Clock D D D Q0 Q1 Q2 Q(N-1) D0 D1 D2 D(N-1) 3

A broadside two-to-one multiplexor

MUX2 N N N Select DT DF Y Select Y0 Y1 Y(N-1) DT0 DF0 DT1 DF1 DT(N-1) DF(N-1)

4

A dual port register file

Write Address Data in Data out A clock N N A Read Address B A Read Address A A Data out B N

5

Read Only Memory (ROM)

The ROM takes A address bits named A0 to A<A-1> and produces data words of N bits wide. For example, if A=5 and D=8 then the ROM contains 2**5 which is 32 locations of 8 bits each. The address lines are called A0, A1, A2, A3, A4 and the data lines D0, D1, ... D7 Address In Data Out Enable Input (active low) Valid data

High-Z

High-Z The ROM’s outputs are high impedance unless the enable input is asserted (low). After the enable is low the

• utput drivers turn on. When the address has been stable

sufficiently long, valid data from that address comes out. The ROM contents are placed inside during manufacture or field programming. Data Out Address In Enable Input (active low) E Addr Data N A ROM PROM

• r

EPROM Access Time Ouput Turnon Time

6

Address In Data Bus Enable Input (active low) Valid data High-Z High-Z Read Cycle - Like the ROM Write Cycle - Data stored internally Read or write mode select Address In Data Bus Enable Input (active low) Data must be valid here to be stored. High-Z High-Z Read or write mode select Data In and Out Address In Enable Input (active low) E Addr Data N A

RAM

R/Wb Read or write mode select

7

G D G D G D G D G D G D

Data

Address Input Binary to unary decoder

WE* CE*

• utput

enable G Q D Transparent latch schematic symbol D G Q Transparent latch implemented from gates. Unlike the edge-triggered flip-flop, the transparent latch passes data through in a transparent way when its enable input is high. When its enable input is low, the output stays at the current value.

8

Refresh Cycle - must happen sufficiently often!

A DRAM has a multiplexed address bus and the address is presented in two halves, known as row and column addresses. So the capacity is 4**A x D. A 4 Mbit DRAM might have A=10 and D=4. When a processor (or its cache) wishes to read many locations in sequence, only one row address needs be given and multiple col addresses can be given quickly to access data in the same row. This is known as ‘page mode’ access. EDO (extended data out) DRAM is now quite common. This guarantees data to be valid for an exteneded period after CAS, thus helping system timing design at high CAS rates.

Multiplexed Address Data Bus Valid data High-Z High-Z Read Cycle (write is similar) Read or write mode select Row Address Col Address Row Address Strobe (RAS) Row Address Strobe (CAS)

Row Address Strobe (RAS) Row Address Strobe (CAS) No data enters or leaves the DRAM during refresh, so it ‘eats memory bandwidth’. Typically 512 cycles of refresh must be done every 8 milliseconds. Data In and Out Multiplexed Address In Row Address Strobe (RAS) RAS MAddr Data N A

DRAM

R/Wb Read or write mode select Row Address Strobe (CAS) CAS

9

Crystal oscillator clock source

33pF Ground 33pF 1M

RC oscillator clock source

Ground C R Vo Vin

10

Clock multiplication and distribution

VCO Clock distribution tree 264 MHz 33 MHz Divide 8 External clock input PLL Circuit Outside the chip Inside the chip

Power-on reset

Ground C R Reset output Supply Active low Vo Vi

11

Driving a heavy current or high-voltage load

Ground R Control input High Voltage Supply EMF diode Power transistor

12

Debouncer circuit for a two-pole switch

A B Output Output A B Gnd +5Volt supply rail Pullup Resistors Bounces Switch 13

ALU and flags register

Function Code 4 N N N Carry In ALU A-input B-input Output C N Z V Flags Clock Flags register

14

ALU and register file

Function Code 4 8 Carry In 8 bit ALU A-input B-input Output 4 bit counter Register file 16 registers

• f 8 bits

4 A 8 D Carry Out Q Din 8 B A Clock source FUNCTION GEN Zero detect 8 FUNCTION GEN for F code for A input

15

Logic Symbol Internal Structure Block Diagram

Address Data N A System Clock Reset Input Interrupt Request Operation Request Read/Notwrite Wait I W R/Wb Opreq R Microprocessor Operation Request Read/notwrite Data Bus Address Bus Bus Control Clock ALU MUX Addresses Dual Port Register File Write Execution Unit Control Unit Instruction Register Instruction Decoder Control Wires To All Other Sections Mux 2 Program Counter Execution address incrementor Clock Clock Clock MUX2 Function code Load or Store System Clock Reset

PC

Reset

OPERAND EA IR

16

D Q GND VCC Broadside latch Broadside tri-state Microprocessor D0 D1 D2 Part of data bus Part of address bus A12 A13 A14 A15 R/Wbar OPREQ Pullup resistors Light emitting diodes (LEDs) Write to leds Read from switches D3 D4 D5 Switches

Example of memory address decode and simple LED and switch interfacing for programmed IO (PIO) to a microprocessor.

17

A small computer

Control Unit Execution Unit + ALU Memory Static RAM 16 kByte UART Serial Port Address bus (16 bits) Data bus (8 bits) (Micro-)Processor Rs232 Serial Connection Register File (including PC) D0-7 D0-7 D0-7 Clock Reset R/Wb Memory Map decoder circuit Often a ‘PAL’ single chip device. A15 A14 A13 R/Wb R/Wb A0-13 Enb Enb Enb 1 K Byte ROM Read Only Memory A0-9 A0-2 R/Wb R/Wb ROM_ENABLE_BAR UART_ENABLE_BAR RAM_ENABLE_BAR D0-7

18

PC Motherboard, 1997 vintage

SIMM 4 SIMM 3 SIMM 2 SIMM 1 COM1 COM2 USB IDE-1 IDE-2 Floppy BIOS ROM Pentium CPU CACHE RAM PSU KYBD PCI1 PCI2 PCI3 ISA 16 BIT SLOTS BATTERY PRINTER Cache Control IDE & Floppy General glue Clock Regulator Main memory DRAM

19

Parallel Port

Address Data device select /cs Strobe Read/Writebar r/wbar Acknowledge Parallel Data Busy D25 Parallel (Centronix) Port Strobe_bar Acknowledge Parallel Data Busy Valid Data For Transfer To Peripheral Device Ready for next data Parallel Port Interface Logic Flow control: New data is not sent while the busy wire is high. CPU BUS SIDE

20

Serial Port (UART)

DO D1 D2 D3 D4 D5 D6 D7 LOGIC 1 LOGIC 0 Start Bit (zero) Stop Bit (one) Address Data chip select /cs Serial Input Serial Output Baud Rate Generator Read/Writebar r/wbar Interrupt Int Voltage convertors 25-Way D connector for Serial Port. Most computers just use a 9 way connector these days.

Flow control: New data can be sent at any time unless either: additional signals are used to indicate clear to send

• r

a software protocol is defined to run on top (Xon/Xoff) by reserving certain of the bytes.

21

Keyboard and/or PS/2 port

+5 Volt Fuse Ground Clock wire Data Wire Power wire Ground wires PS/2 Connector 1 2 3 4 5 6 PS/2 Keyboard/Mouse Cable

• 1. Clock
• 2. Ground
• 3. Data
• 4. Spare
• 5. Power +5Volts
• 6. Spare

22

Canonical synchronous FSM

FSM

Clock Mealy Outputs Inputs D Clock D D D Q0 Q1 Q2 Moore Outputs LOOP-FREE COMBINATORIAL LOGIC BLOCK I0 I1 I(M-1) M I2 CURRENT STATE FEEDBACK STATE FLOPS LOOP-FREE COMBINATORIAL LOGIC BLOCK LOOP-FREE COMBINATORIAL LOGIC BLOCK Moore Outputs Mealy Outputs Inputs

23

Timing Specifications

Clock Data in

D

Q oiutput

Q

Q oiutput Data in Clock Hold time Propagation delay Setup time

24

Typical nature of a critical path

Clock A B C D Setup Margin Period = 1/F Clock D Q D Q A B C D

25

Johnson counters

D Q3 D Q2 D QA Clock

Q1 Q2 Q3 Q1 Q2 Q3

26

Pipelining

Data in

D Q D Q D Q D Q D Q D Q

Synchronous global clock signal Another input Yet another input An output Yet another output Another output still Large loop-free combinatorial logic function Data in

D Q D Q D Q D Q D Q D Q

Synchronous global clock signal Another input Yet another input An output Yet another output Another output still Loop-free combinatorial logic function - second half

Desired logic function Desired logic function - pipelined version. D Q D Q D Q D Q

Loop-free combinatorial logic function - first half

27

Cascading FSMs

FSM

Mealy Outputs Inputs Moore Outputs

FSM

Mealy Outputs Moore Outputs

FSM

Inputs Clock Moore Mealy Inputs

28

An example that uses (badly) a derived clock: a serial-to-parallel converter

D Q D Q D Q D Q Shift Register D Q D Q D Q D Q D Q Five Bit BroadsideRegister Divide by 5 counter Parallel data out Serial in Clock input

29

A D-type with clock-enable

D Clock Data in Q Output Clock enable D Data in Q Output Clock enable Clock CE LOGIC SYMBOL AN EQUIVALENT CIRCUIT 1

30

A Gated Clock

D Master Clock D Synchronous subsystem requiring gated clock J K Enablebar Enable expression

31

Clock Skew

D Q

Delay

D Q

Delay

D Q

Delay Data input Data output QA QB Clock

a) A three-stage shift register with some clock skew delays. D Q

Delay Data input QB

b) System interconnection with clock skews

Delay

c) A solution for serious skew and delay problems ? D Q

Delay QB Delay

D Q

Delay QB Delay Clock

D Q

Delay Data input QB Delay

D Q

Delay QB Delay

D Q

Delay QB Delay Clock

32

Crossing an async boundary

Receiving clock domain Transmit clock domain TX clock RX clock

Guard signal Command or info bus

N

Good to have a second D-type

• 1. The wider the bus width, N, the fewer the number of transactions per second needed and the greater

the timing flexibility in reading the data from the receiving latch.

• 2. Make sure that the transmitter does not change the guard and the data in the same transmit clock cycle.
• 3. Place a second flip-flop after the receiving decision flip-flop so that on the rare occurances when the first

is metastable for a significant length of time (e.g. 1/2 a clock cycle) the second willpresent a good clean signal to the rest of the receiving system.

33

Paths between FSMs w/ derived clocks

FSM

Inputs Clock Input Moore Mealy

FSM

Mealy Outputs Moore Outputs Inputs

FSM

Mealy Outputs Moore Outputs Inputs Moore feedback to parent clock domain Feedforward of

• utputs to son FSM

34

Dicing a wafer

(Chips are not always square)

35

A chip in its package, ready for bond wires

DIE PIN PACKAGE BOND PAD CAVITY

IO and power pads

Connections to and from core logic Pad power supply Pad Electronics Supply Pad Ground Rail Signal Bond Pad Edge of Die Power Rail Ground Pad CORE AREA

36

Die cost example

Area Wafer dies Working dies Cost per working die 2 9000 8910 0.56 3 6000 5910 0.85 4 4500 4411 1.13 6 3000 2911 1.72 9 2000 1912 2.62 13 1385 1297 3.85 19 947 861 5.81 28 643 559 8.95 42 429 347 14.40 63 286 208 24.00 94 191 120 41.83 141 128 63 79.41 211 85 30 168.78 316 57 12 427.85 474 38 4 1416.89

37

A taxonomy of ICs

Standard Parts Semi Custom Full Custom Standard Cell Gate Array Integrated Circuits Masked ASICs Field Programmable Parts FPGA Array Logic (PALs) Commodity Parts General Chip Products

38

Field Programmable Gate Arrays

CLB SWITCH MATRIX CLB SWITCH MATRIX CLB SWITCH MATRIX CLB SWITCH MATRIX CLB SWITCH MATRIX CLB SWITCH MATRIX CLB SWITCH MATRIX CLB SWITCH MATRIX CLB CLB CLB CLB SWITCH MATRIX CLB CLB SWITCH MATRIX SWITCH MATRIX Bond pad IOB Bond pad IOB Bond pad IOB Bond pad Bond pad IOB Bond pad IOB Bond pad IOB

Edge of die

39

A configurable logic block for a look-up-table based FPGA

General inputs Combinatorial function generator D Q D Q Clock input First output Second Output Programmable multiplexers

40

A simple IO block FPGA

Bond PAD Input buffer Input Output Tristate control Output enable Programmable multiplexor 1 Output buffer Connections to central array.

41

Power supply pin Clock signal Clock input General purpose inputs Product line Term line Output pad (can also be input). Output enable product line Ground pin. The cross points in these shaded regions are programmable points Macro- cell Macro- cell Macro- cell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

42

Contents of the PAL macrocell

Input buffer Clock Net I/O Pad Tristate

• utput pad

Programmable multiplexor D-type flip-flop D Q Main input S-of-P Output enable term Feedback to array

43

Example programming of a PAL showing only fuses for the top macrocell

pin 16 = o1; pin 2 = a; pin 3 = b; pin 4 = c

• 1.oe = ~a;
• 1 = (b & o1) | c;
• x-- ---- ---- ---- ---- ---- ----

(oe term)

• -x- x--- ---- ---- ---- ---- ----

(pin 3 and 16)

• --- ---- x--- ---- ---- ---- ----

(pin 4) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx x (macrocell fuse)

44

Delay-power style of technology comparison chart

Delay (ns) Power per gate (mW).

0.1 1.0 10 100 1000 1 10 100 ECL TTL CMOS Lines of constant delay-power product 1980 1990 2000 0.01 0.1 CMOS 1970 CMOS

Technology device propagation power product

• 1977 CMOS

HEF4011 30 ns 32 mW 960 pJ 1982 ECL sp92701 0.8 ns 200 mW 160 pJ 1983 CMOS 74hc00 7 ns 1 mW 7 pJ 1983 TTL 74f00 3.4 ns 5 mW 17 pJ 1996 CMOS 74LVT00 2.7 ns 0.4 mW 1.1 pJ 2-Input NAND gate. 74LVT00 is 3V3. On-chip logic is much faster. 45

Logic net with tracking and input load capacitances

Parasitic input capacitance Track to substrate capacitance proportional to total track length (area) Driving Gate Driven gates

46

An example cell from a manufacturer’s cell library

Simulator/HDL Call

NAND4 Standard Cell

4 input NAND gate with x2 drive

Schematic Symbol

NAND4X2(f, a, b, c, d);

ELECTRICAL SPECIFICATION

Switching characteristics : Nominal delays (25 deg C, 5 Volt, signal rise and fall 0.5 ns)

Inputs Outputs O/P Falling O/P Rising A B C D F F F F (ps) ps/LU ps ps/LU 142 161 165 170 37 37 37 37 198 249 293 326 33 33 33 34 Min and Max delays depend upon temperature range, supply voltage, input edge speed and process

• spreads. The timing information is for guidance only. Accurate delays are used by the UDC.

: (One load unit = 49 fF) Parameters Input loading Drive capability Pin a b c d f Value 2.1 2.1 2.1 2.0 35 Load units Load units Units

a b c d f

Logical Function

F = NOT(a & b & c & d)

Library: CBG0.5um

X2

CELL PARAMETERS

47

Current digital logic technologies

1994 - First 64 Mbit DRAM chip.

• 0.35 micron CMOS
• 1.5 micron2 cell size (64E6 × 1.5 um2 = 96E6)
• 170 mm2 die size

1999 - Intel Pentium Three

• 0.18 micron line size
• 28 million transistors
• 500-700 MHz clock speed
• 11x12 mm (140 mm2) die size

2003 - Lattice FPGA

• 1.25 million use gate equivs
• 414 Kbits of SRAM
• 200 MHz Clock Speed
• same die size.

See www.icknowledge.com

48

Addition of two integers serially, l.s.b first

D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q First operand A Second operand B Serial sum Y Carry Full adder +

let Y = a * 5 in ...

Bit-serial multiplication of an integer by a hardwired constant

D Q D Q D Q D Q D Q D Q Input operand A Serial product Y Carry Full adder +

let y = a*5 in ...

49

Design partitioning: The Cambridge Fast Ring

8 8 8 DRAM

CMOS CHIP

(Standard Part)

ECL CHIP

Isolating transformers Ring Connector VCO (analogue) Interrupt PAL Standard data buffers Address PAL Host Bus 12.5 MHz 100 MHz

50

Design partitioning: An external modem

Telephone line interface Off-hook relay Isolation transformer A-to-D D-to-A Main DSP processor Single-chip processor RS-232 line drivers Computer interface Led indicators Power supply conditioning Ring detector DSP ROM DSP RAM Directional isolator NV-RAM DC power input

51

Design partitioning: A Miniature Radio Module

DAC Carrier Oscillator 2.4 GHz Microcontroller Baseband Modem Antenna Data Interfaces RF Amps IF Amps ADC FLASH memory chip Digital Integrated Circuit Analog (RF) Integrated Circuit Line dri- vers Hop Controller

www.bluetooth.org www.csr.com Multi-chip module or mini PCB

RAM

52

A Very Basic Microcontroller

Microprocessor (8 bit generally) RAM (e.g. 2 Kbytes) OTP EPROM (e.g. 8 Kbytes) Clock Osc Power Up reset Programmable IO Counters and Timers UART I/O wires OR external bus Reset capacitor Clock Serial TX and RX Internal A and D busses

53

LEDs wired in a matrix to reduce external pin count

A B C D E P Q R S T

54

IR Handset Internal Circuit

Battery Scan multiplexed keyboard Single chip containing all semiconductors Clock capacitor Infra-red transmit diodes +

• 55

Scan multiplex logic for an LED pixel-mapped display

Pixel RAM

SCAN MULTIPLEXED DISPLAY MATRIX N bit COUNTER BINARY to UNARY DECODER Row Addr Data lilines (zero for on) CLOCK

A D 2^N col lines One col line is logic one at a time.

56

Addition of psudo dual-porting logic

Pixel RAM

SCAN MULTIPLEXED DISPLAY MATRIX N bit COUNTER BINARY to UNARY DECODER Row

A D Broadside tri-state buffer Write data Write address WE Write strobe bar MUX2 N 57

Use of a ROM as a function look-up table

A to D convertor Look-up table ROM D to A convertor 16 16 65536 by 16 ROM Sample clock 44.1 kHz 12 inch speakers Amplifer A D

58

Use of an SRAM to make the delay required for an echo unit

A to D convertor D to A convertor 16 16 Amplifer A D Static RAM 65536 by 16 bits 16 bit synchronous counter 16 RAMWE RAMOE ADOE Timing generator circuit ADOE RAMWE RAMOE Derived clock, 44.1 kHz 88.2 kHz Read cycle Write cycle Read cycle Clock 88.2 Clock 44.1 RAMWE RAMOE Counter Output

N-1 N N+1 RAM data pins Old sample replay New sample write

59

Merge unit block diagram

DO D1 D2 D3 D4 D5 D6 D7 LOGIC 1 LOGIC 0 Start Bit (zero) Stop Bit (one) Bit spacing is reciprocal of 31.25 kbaud, which is 32 microseconds. + 5V VCC

• Logic level
• utput

Open collector buffer 220R 220R GND 5V VCC LED Photo- transistor +

• Logic level input

220R GND 5V VCC LED Photo- transistor +

• Logic level input

220R

Merged midi output Midi input

• ne

Midi input zero Midi merge function to be designed Clock 1 MHz

module MERGER(out, in0,in1, clk);

MIDI serial data format

9n kk vv (note on) 8n kk vv (note off) 9n kk 00 (note off with zero velocity)

60

MIDI merge unit internal functional units

Serial to par Remove status FIFO Queue Serial to par Remove status Queue Par to serial Insert running status Queue Meger core function Midi In 0 Midi In 1 Merged midi output 8 24 8 24 8 24 24 24 24

61

The serial to parallel converter:

input clk;

• utput [7:0] pardata;
• utput guard;

The running status remover:

input clk; input guard_in; input [7:0] pardata_in;

• utput guard_out; output [23:0] pardata_out

For the FIFOs:

input clk; input guard_in; input [7:0] pardata_in; input read; output guard_out;

• utput [23:0] pardata_out;

input read; output guard_out;

• utput [23:0] pardata_out;

For the merge core unit:

input clk; input guard_in0; input [23:0] pardata_in0; output read0; input guard_in1; input [23:0] pardata_in1; output read1;

• utput guard_out; output [23:0] pardata_out;

input read; output guard_out;

• utput [23:0] pardata_out;

Status inserter / parallel to serial converter are reverse of reciprocal units

62