Introduction to FPGAs Getting Started with Xilinx Digital Design - - PowerPoint PPT Presentation

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Introduction to FPGAs Getting Started with Xilinx Digital Design - - PowerPoint PPT Presentation

Introduction to FPGAs Getting Started with Xilinx Digital Design Everything is represented in two discrete values: 0 and 1 We use low and high voltages to represent these values Use binary arithmetic and boolean math


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SLIDE 1

Introduction to FPGAs

Getting Started with Xilinx

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SLIDE 2
  • Everything is represented in two

discrete values: “0” and “1”

  • We use low and high voltages to

represent these values

  • Use binary arithmetic and boolean

math

Digital Design

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SLIDE 3
  • Converting decimal to binary:

11 / 2 = 5 remainder 1 5 / 2 = 2 remainder 1 2 / 2 = 1 remainder 0 1 / 2 = 0 remainder 1

  • Read it from bottom to top: 1011

Binary Numbers

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SLIDE 4
  • Converting from binary to decimal
  • Every digit represents a power of two
  • Note that we start with 20

Binary Numbers

(1 x 23) + (0 x 22) + (1 x 21) + (1 x 20) = 11

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SLIDE 5
  • Field Programmable Gate Array
  • Hardware that can be customized
  • Can be programmed to do just about

anything you want them to do.

What is an FPGA?

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SLIDE 6
  • HDL (Hardware Descriptive Language)
  • Allows one to create designs using a

text language

  • One “lays out” the design

Verilog

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SLIDE 7
  • Clocks define the time element of a

design

  • Clocks alternate between high and low in

a square wave

Clocks

Time

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SLIDE 8
  • We are only concerned with clock edges

usually

  • Edges are simply where a transition

takes place

Clock Edges

Time

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SLIDE 9
  • We will create a design that counts up
  • n every clock edge
  • Will store the value in a piece of

hardware called a “register” (think memory)

  • We will use an 8-bit number,

representing 28 = 256 different values

A Simple Counter

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SLIDE 10
  • “Black box” – should have inputs and
  • utputs
  • Focus on “what” not “how”

A Simple Counter

Counter

clock counter_value

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SLIDE 11

module counter( clock, counter_value ); input clock;

  • utput [3:0] counter_value;

reg [3:0] counter; assign counter_value = counter; always @(posedge clock) begin counter = counter + 1; end endmodule

The Code

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SLIDE 12

module counter( clock, counter_value ); input clock;

  • utput [3:0] counter_value;

… endmodule

The Code

  • “module” declaration specified what

the inputs and outputs are

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SLIDE 13

reg [3:0] counter;

The Code

  • “reg” keyword makes a register. We use

the bracket notation to specify how big the number is

  • Since we’re using 4 bits, we can

represent 24 numbers, or 16 total numbers

  • 0000, 0001, 0010, 0011, 0100, etc.
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SLIDE 14

always @(posedge clock) begin counter = counter + 1; end

The Code

  • “always” specifies that we want to do

something whenever a change occurs

  • In our case, anytime the clock goes from

low to high, increment the counter

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SLIDE 15

Visualizing The Code

  • Concurrency – Everything happens at
  • nce
  • Verilog code turns into real hardware
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SLIDE 16

Visualizing The Code

module counter( clock, counter_value ); input clock;

  • utput [3:0] counter_value;

endmodule clock counter value

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SLIDE 17

Visualizing The Code

module counter( clock, counter_value ); input clock;

  • utput [3:0] counter_value;

reg [3:0] counter; endmodule clock counter value

c

  • u

n t e r

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SLIDE 18

Visualizing The Code

module counter( clock, counter_value ); input clock;

  • utput [3:0] counter_value;

reg [3:0] counter; assign counter_value = counter; endmodule clock counter value

c

  • u

n t e r

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SLIDE 19

Visualizing The Code

module counter( clock, counter_value ); input clock;

  • utput [3:0] counter_value;

reg [3:0] counter; assign counter_value = counter; always @(posedge clock) begin counter end endmodule counter value

c

  • u

n t e r

clock

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SLIDE 20

Visualizing The Code

module counter( clock, counter_value ); input clock;

  • utput [3:0] counter_value;

reg [3:0] counter; assign counter_value = counter; always @(posedge clock) begin counter = end endmodule clock counter value

c

  • u

n t e r

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SLIDE 21

Visualizing The Code

module counter( clock, counter_value ); input clock;

  • utput [3:0] counter_value;

reg [3:0] counter; assign counter_value = counter; always @(posedge clock) begin counter = counter + end endmodule clock counter value

c

  • u

n t e r Adder

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SLIDE 22

Visualizing The Code

module counter( clock, counter_value ); input clock;

  • utput [3:0] counter_value;

reg [3:0] counter; assign counter_value = counter; always @(posedge clock) begin counter = counter + 1; end endmodule clock counter value

c

  • u

n t e r Adder 1

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SLIDE 23

Tools Of The Trade

  • Xilinx Software – ISE (Integrated Software

Environment)

  • Allows us to create designs
  • Does all the grunt work of turning our

code into physical hardware

  • We program the chip through ISE
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SLIDE 24

Hands On

  • Next session will be a walkthrough of

the hardware

  • We’ll get to program an actual

counter