Development of Optical Interconnect PCBs for High-Speed Electronic - - PowerPoint PPT Presentation

Development of Optical Interconnect PCBs for High-Speed Electronic Systems – Fabricator’s View

2011 IBM Printed Circuit Board Symposium Raleigh, NC, USA November 16th 2011, Time: 10:00-10:30am

Speaker: Marika Immonen TTM Technologies

Outline

• Motivation – Need and Challenges
• Roadmap for Intra-System Optical Interconnects
• Optical PCB Development

– Development Objectives and Target Applications – Polymer Waveguide Technology and Channel Termination – Test Vehicle Description and Results

• Summary
• Future Work

Motivation

• Standard initiatives for higher data rates

– IEEE 802.3ba 40/100G ratified June 2010 – 1st Gen will use 10 Gbps signaling – Improvements in size, power, and diff pair count leads increasing data rates per lane – 25 Gb/s [IEEE & OIF CEI 25G/28 G]; 10-20 Gb/s

[Infiniband, & Fiber Channel]

Sources: Cisco Visual Networking Index - Forecast and Methodology 2007-2012, IEEE 802.3 100G Copper BP TF; Optical Interconnecting Forum (OIF)

• Growing bandwidth demand

– Many studies show 40-50% annual growth in global Internet traffic – High-definition video and high-speed broadband penetration and consumer IP traffic responsible for majority of the traffic growth. [Cisco Visual

Networking Index 2008]

– Enablers: Smart & media devices, social networks, 3D content, Cloud computing and services

• Increasing gap between network traffic and

hardware development

– Network traffic 2x in 18 months – Server I/O 2x in 24 months

Copper Backplane Challenges

• Some challenges for 25 Gb/s/lane implementation

– Fabrication: Copper roughness, back drilling stub removal, moving to low & ultra-low loss material set & processes – Well controlled Electrical/Mechanical parameters

• Flatness; Hole locations; Thickness variations
• Copper geometries & tolerance vs. Impedance, Attenuation, Propagation delay

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Copper will be used as long as competitive alternatives are not available – Power Consumption: Goal to keep less 1.5x of power of 10Gb/s [OIF CEI 25/28] => Challenging – Cost: Ultra-low loss materials 3-6x FR4; additional chips (equalization, amplification) increase cost – Termination: challenging to design (low cross-

talk, noise), difficult to maintain form factors &

high density – Need clear understanding of yield detractors: yield/cost vs. design trade-offs

Optics Will Be A Solution to Mitigate Challenges

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• High-Speed interconnect is costing

more power and money

• A terapipe, bi-directional Tbps interconnect

– Copper transceivers: $3500/year

• Each 100G link consumes 10W each

(1kW/Tb)

– Traditional Optics: $700/year

• Each 10G XFP (10km) consumes 2W

(200W/Tb)

– VCSELs: $70/year

• Each 10G VCSEL consumes 0.2W (20W/Tb)

– Silicon Photonics: $70/year

• Each 10G Si-Pho link consumes 0.2W

(20W/Tb)

Speed is only one metric, the main drivers for optics are capacity over distance, lower power comsumption, bandwidth density and cost

– IEC “Optical Backplane Roadmap” 86/374/DC 2010

20% reduction in power consumption

Power consumption of 10 Tbps Electrical vs. Optical Router

– Kotura, “The Path to 1 TbE” Ethernet Summit Feb-2011

Cost of a Terapipe Over 5 Years

98% reduction in cost

Power Consumption for Interconnect Operating Costs

Optics Will Be A Solution to Mitigate Challenges

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• Cross-Talk

– Copper: Higher frequency signals => wider pitch: 3x signal speed => 3x pitch – Frequency 2x leads 6 dB increase in crosstalk – Photons: Isolation of few microns enough

• Photons do not suffer EMI

Bandwidth Density [Gbps/mm2]

Optical Electrical

IBM TTM

Core [µm] Pitch [µm] Density [Gbps/mm] Optical vs. copper 50x50 250 40 1,4 50x50 100 100 3,5 35x35 62,5 160 5,6

Waveguide Microstrip

Optical=6x electrical [Gbps/mm2]

• High Speed Design Challenges, Cost and Complexity

– Signal traces with highly controlled impedance, via holes, and connectors are adding cost

– Photons: Frequency independent loss and design

Optical Interconnects for Short Reach Applications

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• Applications per link length

– Within Data Center: 100-300 m – Rack-to-Rack: 20-30 m – Most links in DC – Intra-Rack : < 10 m – Intra-Box links: < 1-2m – FO links emerging

• Server/HPC Environment

– “Everyone needs optical interconnect with low power, low cost and high density”

• One size fits all does not meet the

requirements in this environment

• Requirements vary per application

– Link length vs. cost vs. power consumption

• vs. density

– Various physical link implementations, connector and device form-factors needed

Opto-electronic module Optical circuit board Optical backplane

＜商品化段階＞ Discussion field in JWG9

Fibre cable Optical connector IEC TC86 field for standardization Opto-electronic module Optical circuit board Optical backplane

＜商品化段階＞ Discussion field in JWG9

Fibre cable Optical connector IEC TC86 field for standardization

“Intra-Box” “Out-of-Box”

Image: Sunway BlueLight MPP, National Supercomputer Center in Jinan, China Image: Avago

• - $/Gbps
• - $/Inch of board edge
• - Potential BW off ASIC
• - Watt/Gbps or pJ/bit

– IEEE Next-Gen 100Gb/s Optical Ethernet Study Group

Optical Intra-System Link Evolution

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Fiber links (Single) Flex Shuffle Backplane (Fiber flex) Active Optical Cables 1-10 Gb/s (SFP+) Fiber Backplanes Fiber Optic Engines (Parallel) 5-25 Gb/s Fiber-Waveguide Backplanes Waveguide Backplanes Fiber-less Engines (Highly parallel) > 12.5 Gb/s 1st Gen 2nd Gen 3rd Gen 1990 1995 2010 2015 2005 Number of links, Integration level, Functionality

RACK-TO-RACK BOARD-TO-BOARD BACKPLANES AND ON-BOARD

Density, Capacity, Complexity 2012

Embedded Waveguide Architecture and Building Blocks

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• 2. Optical Channel

Tx/Rx : VCSEL, DRV, PD, TIA

CARD CARD BACKPLANE

• 3. Optical Connectors with

functions e.g. 90° beam deflection

• 1. Optical Engines with

Interface to waveguides

1 1 2 3 2 3

Logic IC Tx/Rx : VCSEL, DRV, PD, TIA Logic IC

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Development Objectives Optical/Electrical Circuit Board Technology

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• Hybrid passive PCB with optical and

electrical interconnects

• Optical manufacturing methods and

tolerances compliant with conventional PCBs

• Passive optical alignment and simple

assembly (optical device to connector, connector to

board, connector to connector)

• Pluggable optical connectors with

reasonable alignment tolerance

• Cost comparable to electrical solution
• High reliability and long-term stability

• Optical Routing Requirements

– Point-to-point links – Link length: 130-200 mm – Cascading bends

• Negative and positive cascading 90° bends
• Multiple cascading bends per link
• RoCmin 17 mm

– Crossovers

• Waveguides intersect in one or more

positions along the channel

• Angles 130° to 160° (40° to 70°)

Optical Waveguide Routing Layout And Components

BACKPLANE/ MIDPLANE Optical Electrical CARD CARD CARD

Network Storage Midplane

R.Pitwon et al.: “Design and Implementation of an Electro-Optical Backplane with Pluggable In-Plane Connectors”, SPIE 7607-18, 2010.

Production Test Vehicle Description

• Optical/Electrical Mixed Signal Board

– Generic test bed with multiple waveguide passive components – Designed for parallel optics l=850 nm VCSEL /PD 12-channel unidirectional or 4+4 bidirectional Engines – Optical waveguide signal layer

• Multi modal type with numerical aperture (N.A.) matching MMF
• Square step index profile in multiple core sizes and pitch

– Core: 25x50µm2, 50x50µm2, 70x50µm2; Pitch: 250µm, 100µm

– Optical circuit layout with multiple design features & functions : Straight, cross-overs, bend waveguides – Channel termination and optical I/O coupling

• Flat end I/O and 45° out-of-coupling micro-mirrors

– Variations in board construction and layer count

• 2+W and 2+W+2 (W=waveguide)
• High-Tg Std. loss FR-4 (baseline); Mid-loss halogen-free base

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Fabricated OE PCB Module : 2+W+2

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Connector test sites Embedded Optical Layer Construction : 2+W+2 Optical I/O – Board build: 2+W+2 (W=waveguide) – Board thickness 2.0 mm – Optical layer thickness: 115 µm – Waveguide width: 25’ 50’ 70 µm – Channel pitch: 100’ and 250 µm – Integrated 45-deg beam couplers Waveguides

Waveguides W=25’ 50’ 70 µm, Pitch=100 µm, 250 µm

• Physical Characterization

– Parameters: Dimensions, uniformity, alignment accuracy , surface

• roughness. Tools: Optical, LSCM, SEM

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L/S 70/30 µm, Pitch 100 µm L/S 50/50 µm, Pitch 100 µm

L/S 50/250 µm, Pitch 250 µm L/S 25/100 µm, Pitch 125 µm

L/S 50/200 µm, Pitch 250 µm

Side Wall Roughness vs. Channel Loss

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λ= 850 nm, Core 100µmx100µm, ncore=1,56, nclad=1,49 (NA=0.46)

Source: It-Infomation Technology 45 (2003), 79-86

Core ”Micro” roughness : < 5 nm Cladding ”Macro” roughness (L=240 µm) Core ”Macro” roughness (L=300 µm) Ra < 25 nm Ra < 30 nm White light interferometer (Wyko NT 2000)

Fabrication Requirements

• Process requirements

– Cost-effective processes scalable to standard panel sizes – Optical material coatable by conventional processes

• Thickness control : < 5 µm

– I-line exposure compatible in ambient conditions

• High resolution soda lime or quartz mask technology
• May need soft contact, proximity or projection

– Processing needs clean room environment – Curing temperatures compatible with laminate loading

• Material selection criteria

– Low intrinsic absorption at operational wavelength, typ. l = 830-860 nm – Tunability of refractive index to N.A. 0.2-0.3 – High thermal, mechanical & chemical robustness and compatibility to CCL materials

• Withstand thermal processes, lamination, solder reflow,

humidity, chemicals during processing and service

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Termination, 1st Level: Chip-to-Waveguide

17 Indirect coupling with micro-optics

SMT packaged OEs 90-deg beam turn

Loosest tolerance

Complex I/O

”Chip-like approach”

Low loss m-optics and beam turn No comm.OE- pkgs

Indirect coupling without micro-optics

Flip chip OEs 90-deg beam turn Simple I/O FC OEs available

High accuracy critic.

Low loss beam turn

Direct coupling

OE-chip in cavity or plugg-in rod No beam turn Simple I/O Low loss I/O WG end face critic.

Termination, 2nd Level: Card-to-Backplane

Waveguide Waveguide BACKPLANE CARD MT MT

1st Gen. Backplane Connector Flexible waveguide terminated by standard MT- connectors; 90° bend by WG 2nd Gen. Backplane Connector Connector with coupling device for mid-board vertical access; 90° by built-in deflection optics

Development collaboration in HDPUG (High Density Interconnect User Group) Consortium (2010-)

Sources: B.Booth “HDPUG Opto-Electronic Test Vehicle 1” Feb 2011; D.Morlion et al. “Optical Backplane Interconnect” June 2011

Polymer Waveguide Thermo-Mechanical Stability

• No significant changes in intrinsic attenuation or refractive index
• Environmental: 85°C /85%-RH > 4500 h
• Withstand temperatures in excess of 250 °C (Solder reflow)
• 5-wt% loss at 522°C

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Commercial siloxane-based material

85°C/85% rH Reliability Performance on FR4 Thermal Stability (TGA)

Summary and Future Work

• Potentials for lower power consumption and higher channel density are

key drivers for optical interconnects intra-box

• Manufacturing of waveguides, out-of-plane couplers and routing

components on PCBs in panel scale processes is challenging, yet possible

• Efficient coupling structures and connector solutions and optical engines in

packages with interface to waveguides are needed to provide end-to-end

• ptical links for drop-in replacement for Users
• Reliability system-level needs to be qualified according user specific

requirements

• For commercial break-though

– Supply chain across the industry to support polymer waveguide technology – Clear product roadmaps from End-Users and OEMs for applications – Cost/performance comparable to copper by High/Volume fabrication, low-cost device technologies and end applications 20