Module PCBs and Teststands Keti Kaadze, Kansas State University, L4 - - PowerPoint PPT Presentation

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Module PCBs and Teststands Keti Kaadze, Kansas State University, L4 - - PowerPoint PPT Presentation

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Module PCBs and Teststands Keti Kaadze, Kansas State University, L4 Manager 402.4.4.1.3 Module PCBs 402.4.4.2.1 Module teststands November 29, 2017 Module PCBs The same Module PCBs will be used in CE-E and CE-H parts Design is

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Module PCBs and Teststands

Keti Kaadze, Kansas State University, L4 Manager

402.4.4.1.3 – Module PCBs 402.4.4.2.1 – Module teststands

November 29, 2017

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§ The same Module PCBs will be used in CE-E and CE-H parts

§ Design is led by CERN group with some contribution for FNAL & KSU engineers

§ Full testing of each PCB needs to be carried out before assembling it into module

§ Test-stands for handling large quantities of PCBs as well as a single-module tester are needed for full production

Module PCBs

Ke# Kaadze, 2017 November 29 The module PCB, the hexaboard Module PCBs and Teststands

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§ Hexaboard contains several HGCROC § Using board-to-board connectors for connecting to motherboard

§ Same connector will be used to connect to board tester

Module PCBs

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Conceptual Design for Module PCB Tester

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§ The test procedure will be refined as we advance on HGCROC and module PCB design

§ Validation of HGCROC

  • Basic check that we can read and write registers
  • Exercise internal charge injection functionality

§ PCB Noise measurements

  • Pedestal measurement for each channel
  • Check for correlated noise levels

§ Verify that trigger output is appropriate for data during charge- injection tests § C-V scans

  • Confirms wire-bonding and sensor profile
  • Identify problems in PCB or anywhere in module

Test Procedure

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  • Full custom board or COTS FPGA board with custom mezzanine card
  • Ethernet connectivity to computer
  • Low voltage Control and monitoring
  • High voltage control and monitoring (800v)
  • Slow control (I2C)
  • Generate timing, control and calibration signals
  • Receive e-Links from HGCROC ASIC (1.28 Gb/s)
  • Low Density Module
  • 12 trigger e-Links
  • 3 DAQ e-Links
  • High Density Module
  • 18 trigger e-Links
  • 6 DAQ e-Links
  • Scale single test board to test stand
  • COTS temperature chamber with dry air purge
  • 25 Modules per test cycle

Conceptual Design

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Module Test Board Block Diagram

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§ Plan

§ The detector will operate at -30C § The U.S. will be responsible building about 12000 silicon modules

  • Testing procedure will be common between different institutions

contributing to this task: KSU, TTU, CMU, UCSB, and FNAL

§ Requirements for testing

§ Validation and functionality tests needs to be carried out before and during thrermal cycling, before PCBs are assembled into modules § Aim completing testing of full production within one year -- requires a test-stand to handle at least 50 PCBs per day § Perform testing in a clean room § Important starting point – develop and validate test-stand for testing prototype 1 PCBs, O(100) in quantity

Requirements

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§ We have 50 m2 class 10000 (ISO 7) clean room

§ Similar cleanroom facilities will be present at module and cassette factories, wherever we will work with unsealed modules

§ Thermal Cycler – currently considered: BTZ-475 (A) model from ESPEC

§ Sufficiently large volume: 4 cu. ft. § Temperature range: -70°C to 180°C § Humidity control § Computer interface § Similar cycler will be used at module and cassette factories

§ Develop tester board for testing module PBCs § Develop software for test-stand

Requirements for Test-Stand

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Module Test Board Block Diagram

Ke# Kaadze, 2017 November 29 Test system scaled for 25 modules Module PCBs and Teststands

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§ The development of test board is directly related to

§ Development of HGCROC § Design of module PCB

§ Thermal cycling and test procedures will be common between KSU test-stand and module assembly sites

§ Testing board will be developed as common effort of KSU/FNAL/ UCSB group § Test-stand software will be a common effort of KSU/Baylor U. group

Interfaces

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R&D and Engineering

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§ Personnel

§ Physicists:

  • Faculty: K. Kaadze, Y. Maravin
  • Postdoc: A. Mohammadi
  • G student: D. Kim
  • UG students

§ Engineers: Russell Taylor, Stephen Corkill

  • Developed test board for Phase I pixel TMB
  • Developed LED Pulser board for Phase I HCAL FE upgrade

§ Technician: David Huddleston

Institutional and Personnel Involvement

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§ Preparation of module PCBs and test-stands is has started

§ Development of HGCROC and module PCB design is an important input § Preparing test-stands to be able to test and verify full production

  • f module PCBs
  • Develop test-board to perform necessary tests
  • Obtain and setup thermal cycler
  • Develop necessary software

§ Timescale

§ First prototype testing – 2018-2019 § Full production testing – 2020-2022

Conclusion and Outlook

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