Obstacle-Aware Length-Matching Bus Routing Yan and Zhi-Wei Chen - - PowerPoint PPT Presentation

Obstacle-Aware Length-Matching Bus Routing

Jin-Tai Yan† and Zhi-Wei Chen‡ † Department of Computer Science and Information Engineering ‡ College of Engineering

ISPD-2011

Outline

 Introduction  Problem Formulation  Problem Formulation  Obstacle-Aware Length-Matching Bus Routing

 Obstacle-Aware Region Partition in Routing Grids  Obstacle-Aware Region Partition in Routing Grids  Obstacle-Aware Shortest-Path Generation  Iterative Length-Matching Path Generation

 Experimental Results  Conclusions

2

Routing in PCB

 Three processes in PCB routing

E R i

g

• 1. Escape Routing
• 2. Untangling Processing
• 3. Bus Routing

1 4 2 2 3 1

1 4 2 3 1 4 2 3 2 3 1 4 2 3 1 4

Pin array

3 4

Escape routing Bus routing Escape routing Untangle Untangling

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PCB Routing Challenges

 More than thousands of pins are involved

in modern PCBs

g g

in modern PCBs.

 Physical “obstacles” on PCB

 Component mounting pads: DIP / SMD  Pre-route predictions: analog / TTL design

reservation

 Various design constraints  Various design constraints

 Layer constraints  Length matching: each routed net must be

bounded within specific wire length bounded within specific wire length

Source from : http://www.pc01.cn/

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Previous Works

 BGA-Route  T. Yan and M. D. F. Wong, “BSG-Route: A length-matching router for

general topology,” ICCAD,2008.

 Limitations: no obstacle constraint / remainder area in BSG cells  US Routing  Y. Kohira et. al, “A fast longer path algorithm for routing grid with

• bstacles using biconnectivity based length upper bound,” ASPDAC,2009

 Limitations: high time complexity / optimal solution is not guaranteed  Limitations: high time complexity / optimal solution is not guaranteed  CAFE-router  Y. Kohira et.al, “CAFE router: A Fast Connectivity Aware Multiple Nets

Routing Algorithm for Routing Grid with Obstacles ” ASPDAC 2010 Routing Algorithm for Routing Grid with Obstacles, ASPDAC,2010

 Limitations: length-matching with high length error

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Motivations

 Limitations in the previous works

1 Without consideration of obstacles

• 1. Without consideration of obstacles
• 2. Length-matching with length error

 An efficient length-matching approach for bus routing  An efficient length matching approach for bus routing

• 1. Bus routing with considering obstacles
• 2. More accurate result under the constraint of length-matching

g g

6

Preliminary

 Routing area in a single layer can be represented by a set of routing grids



An arbitrary-shaped obstacle can be form by a set of routing grids (drawn by black)

 Grid-based routing path for a net  Grid based routing path for a net



Two grids are specified as the locations of the start and target terminals, S and T



A path connects S and T by using horizontal or vertical segments and passes each available grid at most once



The length of a connecting path is defined as the number of passed grids in the routing



The length of a connecting path is defined as the number of passed grids in the routing path

 Flip operations for path detouring



R-flip: a partial path can be detoured by using adjacent routing grids and inserting a detouring path, P’



C-flip: a partial path, P, can be replaced by using another partial path, P’, where the length of P’ is larger than that of P

T T P’ T T P’ P

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S S S S

Problem Formulation

Input

 Two sequential sets of start and target terminals of r nets in a bus

q g

 Routing panel is divided into a mxn routing grids with s obstacle grids  Each net, i, has its connecting length of the shortest path, di

Constraints

Constraints

 Length constraints, l1, l2,...,lr are given to satisfy the timing constraints

s mn l

• r

d l

r i i i i

  



1

No Solution!! No Solution!!

 Non-crossing between any two pair of nets

i i

 1

Solution available!! Solution available!!

s mn l

• r

d l

r i i i i

  

 1

 Non crossing between any two pair of nets

Objective

 The length-matching paths of r nets are generated in the bus

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Example p

1 2 3 4 1 2 3 4 4 5 6 4 5 6 1 2 3 4 1 2 3 4

20x18 routing grids; 82 obstacle grids; length constraints = 46

4 5 6 4 5 6

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0x 8 ou g g ds; 8 obs ac e g ds; e g co s a s 6 (d1=28, d2=28, d3=28, d4=28, d5=,28 d6=34)

Design Flow g

INPUT:

• 1. Start and target terminals for

b ti Iterative Length-Matching Path bus routing

• 2. Length-matching constraints in

a bus Generation Diffusion-based Longest Path Generation Obstacle-Aware Region Partition inside Routing Grids Internal Length-Matching Path Modification Obstacle-Aware Shortest-Path Generation Diffusion-based Shortest Path External Length-Matching Path Modification OUTPUT: Obstacle-aware length-matching b i l Generation Convergence-based Shortest Path Generation

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bus routing result Path Generation

Region Definition g

 Outer Boundary : minimum

covering rectangular

1

covering rectangular boundaries

 Including all the routing grids:

1 2 3 4 5

available & obstacle grids

 Extended lines on hor. and

vert boundaries of obstacles

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• vert. boundaries of obstacles

 Independent region: hor. or vert.

extended line

1

1.

Two obstacle boundaries

2.

One obstacle boundary and one

• uter boundary

2 3 4 5 6

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• uter boundary

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Iterative Obstacle-Aware Region Partition g

 Partition process

Step 1: If all the routing grids are assigned into independent regions p g g g p g  process done Step 2: According to the extended lines of obstacles and outer boundary, independent region can be found independent region can be found. Step 3: Take the found independent regions as newly obstacles, go to Step 1

 Merging process

 If any independent region is able to be horizontally or vertically merged

with its adjacent independent region, merging with their adjacent regions

 Regions including start or target terminals are defined as start  Regions including start or target terminals are defined as start

region and target region

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Partition & Merging Process

1 2 3

IR1 IR IR3 IR IR9 R3 R11 R1 R

4 5 6

IR2 IR8 Rs IR4 IR12 IR14 R2 R4 R8

1

IR5 R5

2 3 4 5 5

IR6 IR10 IR11 IR13 RT R6 R7 R8 R9

13

6

IR7 R10

Adjacent Graph Construction j p

 Adjacent graph, G(V, E) : an undirected edge-weight graph

 Any Vi, in V represents a partitioned region, Ri.  Any Ei,j, in E represents the adjacent relation between two partitioned regions, Ri

and Rj, and the edge weight, wi,j, represents the allowable net capacity between Ri and Rj.

1 2 3 4 5 6

R3 R11 R1 Rs

V11 V3 V1 2 2

R2 R4 R8

VS V8 V2

3

VT 1 2 6 1 3 6 V4 2

1 2 3 4

RT R5 R8 R9

2

V7 V10 V6 1 4 1 V5 1 1 V9 4 2

14

4 5 6

R7 RT R10

10 6

Flow-Based Path Generation

 According to the adjacent graph, with VS and VT, the

number of maximum flow(routed path), M, can be number of maximum flow(routed path), M, can be

• btained by performing maximum-flow algorithm

 Un-routable condition

 The flow, M, is smaller than the number of nets, r, in a bus

 Routed path assignment

 M fl

f 1 t M d t f 1 t d M ≥

 M flows, form 1 to M and r nets, from 1 to r, and M ≥ r  Balanced distribution expression

V V3 V1 2 2 V1

1

fi = 1 + , if 1≤ i ≤ r (i − 1)(M − 1) r - 1

VS V8 V2

3

VT 1 3 1 2 1 4 3 V5 1 V9 3 2 V4

1

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1 1 V5 1 V6 V7 V10

Assigned Region Relations g g

 Three relations between net and its assigned routed region

1.

Private region



O l t i i d i t thi i  All ti id i id thi i



Only one net is assigned into this region  All routing grids inside this region are only used by the route of the net

2.

Share region



Without any net is assigned into the region  All routing grids inside this region b d b ll ibl t can be used by all possible nets

3.

Public region



Some nets are assigned into this region  All routing grids inside this region can be used by the routes of these assigned nets

Assign region path :

 Net1 Net2 : V  V  V  V  V

VS V3 V1 2 2 2 4 V11

 Net1, Net2 : VS

V1 V3 V8 VT

 Net3 : VS  V2  V4  V8  VT  Net4, Net5 : VS  V2  V5  V9  VT  Net6 : VS  V2  V5  V9  V6  V7  V10  VT

V8 V2 VT 1 3 1 1 3 V5 1 V9 3 2 V4

16

1 1 V6 V7 V10

Initial Obstacle-Aware Path Generation t a Obstac e wa e at Ge e at o

 Objective: determine the routing path inside the assigned

region for all nets

 Two-phase shortest path generation

• 1. Diffusion-based shortest path: sequentially generate the shortest path

for all nets

 First and last of un-routed nets are routed firstly  Route as the outer routing grids as possible  The routed nets are regarded as obstacles

g

• 2. Convergence-based shortest path: integrate the available routing grids

together and distribute in the outer routing area

 Routing with reverse routing order in the first phase

g g p

 Reassign the routing grids as convergent as possible 17

Example of Initial Path Generation p

1 2 1 2 3 4 5 6 3 4 5 6 1 1 1 2 3 4 5 1 2 3 4 5

18

6 6

Iterative Length-Matching Path Generation Iterative Length Matching Path Generation

 Three sub-processes for length-matching path generation

1.

Diffusion-based longest path generation

2

Internal length matching path modification

2.

Internal length-matching path modification

3.

External length-matching path modification

 Diffusion-based longest path generation

 The first and the last nets are firstly considered to generate their diffusion-based

y g longest paths.

 A path along the outer boundary and adjacent obstacles.  Go through the regions on its region path and available share regions.

1 1 2 3 4 5 6 2 3 4 5 6 1 2 3 1 2 3

19

3 4 5 6 3 4 5 6

Internal Length-Matching Path Modification Internal Length Matching Path Modification

 Objective: modify the diffusion-based longest path result

to satisfy the given length constraint to satisfy the given length constraint

 Three possible conditions

• 1. Equal to length constraint

q g

 Two assigned length-matching pats will be treated as obstacles  Process the next pair of un-routed nets

2 Larger than length constraint

• 2. Larger than length constraint

 Shorten the partial or full paths inside the share regions

• 3. Smaller than length constraint
• 1. Detour the partial or full paths inside the regions

 Private region > Share region > Public region

• 2. Detour operations: R-flip / C-flip

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• 2. Detour operations: R flip / C flip

Example of Internal Path Modification Example of Internal Path Modification

1 1 2 3 4 5 6 2 3 4 5 6 1 2 1 2 2 3 4 5 6 2 3 4 5 6

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External Length-Matching Path Modification External Length Matching Path Modification

 Objective: modify the detour path without satisfying the

given length constraint after internal pat modification given length constraint after internal pat modification

 R-flip and C-flip operations on the other public region to satisfy

the given length constraint

1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 1 2 3 4 5

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5 6 5 6

Analysis of Time Complexity y p y

 Obstacle-aware region partition inside routing grids − Partitioning obstacle-aware regions: O(s2)

Adj h i O( )

− Adjacent graph construction: O(s)  Obstacle-aware shortest-path generation − Finding the maximum flow in adjacent graph: O(s3)

F ibl i th i t f ll th t O( )

− Feasible region path assignment for all the nets: O(rs) − Generating diffusion-based and convergence-based shortest path: O(mn)  Iterative length-matching path generation

Generating two diffusion based longest path in each iteration: O(m+n)

− Generating two diffusion-based longest path in each iteration: O(m+n) − Internal and external length-matching path modification: O(l) − l: the given maximum length constrain

Ti C l i O(

3)

Time Complexity: O(r(m+n+l)+s3) r( r(m+n+l m+n+l) ~ ) ~ mn mn

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Time Complexity: O(mn+s3)

Experimental Results p

 Experimental environment



PC: Intel Quad Core 2.66GHz with 2GB memory Programming language : C++ language



Programming language : C++ language

 Two test examples are from the previous published paper -- CAFÉ router  The information of two test examples and the results of comparison show as following :

Circuits Area #Obstacle Grids Number of Nets Length Constraint Data1 28x28 13 4 100 150 Data2 61x130 3441 13 251 301 Example Length constraint CAFÉ Router Our Routing Length Error CPU Time(s) Length Error CPU Time(s) D 1 100 0.35(100%) 0.08(22.9%) Data1 150 10 0.42(100%) 0.09(21.4%) Data2 251 10 25.63(100%) 4.96(19.4%) 301 6 26.85(100%) 5.28(19.7%) Total 26 53.25(19.5%) 10.41(19.5%) 24

Data2 Results

Length constraint = 251

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Conclusions



Signal propagation delays on PCBs are requested to meet the timing constraints with very high accuracy timing constraints with very high accuracy



Based on obstacle-aware region partition, obstacle-aware shortest path generation and two detouring operations, an efficient approach is proposed to generate the length-matching paths

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Th k f tt ti !! Thanks for your attention!! Q&A

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