UT DA DSAR: DSAR: DSA aware Routing with DSA aware Routing with Simultaneous DSA Guiding Simultaneous DSA Guiding Pattern and Double Patterning Pattern and Double Patterning Ass Assignment ignment Jiaojiao Ou 1 , Bei Yu 2 , Xiaoqing Xu 1 , Joydeep Mitra 3 , Yibo Lin 1 , David Z. Pan 1 1 ECE Department, University of Texas at Austin 2 CSE Department, CUHK 3 Mentor Graphics Inc. 1
Outline Outline Introduction Problem formulation Detailed routing algorithms Experimental results Conclusion 2
Intr Introduction: oduction: Technology Technology Scaling Scaling Opto Connect eNVM EUV DSA Transistors EUV LELE CNT 3D IC VNW Graphene Patterning SAQP EUV EBL Interconnect SADP HNW Complexity [Courtesy ARM] LELELE LELE EUV FinFET W LI Cu Doping Planar CMOS LE 10 nm 7 nm 5 nm 3 nm AI / Cu / W wires 2005 2010 2015 2020 2025 3
Technology Technology Scaling: M Scaling: More Mas ore Masks ks Via density increases Triple/Quadruple patternings are required • Placement error problem • Cost increases More via: 1D design Metal 2 Metal 3 Via Mask 1 Mask 2 Mask 3 Mask 4 (a) Original layout (b) Via layer with quadruple patterning 4
Motivation Motivation of DSA of DSA on Via on Via Layer Layer Reduce mask number by grouping vias in the same guiding pattern Reduce 2 mask with DSA 5
Consider Consider DSA DSA during Routing during Routing 1 Initial detailed routing without DSA consideration 3 masks are required 6
Consider Consider DSA DSA during Routing during Routing 2 Initial detailed routing without DSA consideration 3 masks are required Reroute n1 and n3 7
Consider Consider DSA DSA during Routing during Routing 3 Initial detailed routing without DSA consideration 3 masks are required Reroute n1 and n3 Reduce 1 more mask 8
Previous Previous Works Works DSA-aware detailed routing for via layer optimization [Du+, SPIE’14] Resolve conflicts and infeasible via patterns during rip-up and reroute with negotiated congestion based scheme Incapable to handle DSA with multiple patternings More wire length may be introduced Redundant Via insertion consideration [Lin+, ASPDAC’17] Simultaneously consideration of redundant via insertion and guiding template feasibility Increase redundant via insertion rate Multiple patterning for via is not considered, not compatible for 1D design 9
Problem Formulation: Problem Formulation: DSAR DSAR DSA and double patterning aware detailed routing Input: ▷ Netlist with source/target pins ▷ Feasible DSA patterns ▷ Design rules Output: ▷ Minimize wirelength, unroutable nets ▷ DSA-DP compatible via layer 10
Design Design Rules Rules DSA design rules Forbidden Via distribution Metal 2 Metal 3 Via Cut mask More complex guiding templates 11
Pre Pre-rout route N e Net Planning et Planning - 1 Construct conflict graph Vertices: bbox corners Edge weight: DSA friendly? 1: 5 12
Pre Pre-rout route N e Net Planning et Planning - 1 Construct conflict graph Vertices: bbox corners Edge weight: DSA friendly? 1: 5 13
Pre Pre-rout route N e Net Planning et Planning - 1 Construct conflict graph Vertices: bbox corners Edge weight: DSA friendly? 1: 5 14
Pre Pre-rout route N e Net Planning et Planning - 1 Construct conflict graph Vertices: bbox corners Edge weight: DSA friendly? 1: 5 15
Pre Pre-rout route N e Net Planning et Planning - 1 Construct conflict graph Vertices: bbox corners Edge weight: DSA friendly? 1: 5 16
Pre Pre-rout route N e Net Planning et Planning - 1 Construct conflict graph Vertices: bbox corners Edge weight: DSA friendly? 1: 5 17
Pre Pre-rout route N e Net Planning et Planning - 1 Construct conflict graph Vertices: bbox corners Edge weight: DSA friendly? 1: 5 18
Pre Pre-rout route N e Net Planning et Planning - 1 Construct conflict graph Vertices: bbox corners Edge weight: DSA friendly? 1: 5 19
Pre Pre-rout route N e Net Planning et Planning - 2 Conflict graph constraints At most 1 corner of each net 20
Pre Pre-rout route N e Net Planning et Planning - 2 Conflict graph constraints At most 1 corner of each net Corners cross the pins of other nets 21
Pre Pre-rout route N e Net Planning et Planning - 3 Conflict graph constraints At most 1 corner of each net Corners cross the pins of other nets Conflict graph bipartization Pre-determine (estimate) the routing paths for nets 22
Pre Pre-rout route N e Net Planning et Planning - 3 Conflict graph constraints At most 1 corner of each net Corners cross the pins of other nets Conflict graph bipartization Pre-determine (estimate) the routing paths for nets Minimize deleted vertices from conflict graph • DSA unfriendly vertices 23
Pre Pre-rout route N e Net Planning et Planning - 4 Net ordering for undetermined nets More WL Smaller bbox (HPWL) Overlaps Route b first Route a first 24
Detailed Detailed Routing Routing - 1 Routing graph model Routing box All vias are One color Via inserted forbidden assignment 25 forbidden
Detailed Detailed Routing Routing - 2 Routing box state update Nearby routing box update Example Empty via Green via Red via Red via is forbidden All via forbidden grid Green via is forbidden M2 M3 26
Detailed Detailed Routing Routing - 3 Routing scheme Negotiated congestion based A* search 27
Detailed Detailed Routing Routing - 3 Routing scheme Negotiated congestion based A* search 28
Post Routing Post Routing Optimization Optimization Assign DSA guiding patterns Minimize DSA groups and conflicts Edge bipartization 29
Post Routing Post Routing Optimization Optimization Assign DSA guiding patterns Minimize DSA groups and conflicts Edge bipartization 30
Experimental Experimental Setup Setup Implemented in C++ 3.4GHz Linux server, 32GB RAM ILP solver: GUROBI 6.5 OpenSparc T1 design: M2, M3 for routing [Du+,SPIE’14], 1D router 31
Routing Result Routing Result Comparison Comparison 70000 600000 60000 1% better 1D router 500000 20% better SPIE’14 50000 400000 40000 300000 30000 200000 20000 100000 10000 0 0 ecc efc ctl alu div top ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR Conventional 1D router Du+,SPIE'14 DSAR (a) Number of Vias (b) Wirelength 300 5000 250 4000 200 3000 150 2000 100 1000 50 0 0 ecc efc ctl alu div top ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR Conventional 1D router Du+,SPIE'14 DSAR (c) DSA conflicts (d) CPU(s) 32
Routing Result Comparison Routing Result Comparison 70000 600000 60000 1% better 1D router 1% overhead 1D router 500000 20% better SPIE’14 15% better SPIE’14 50000 400000 40000 300000 30000 200000 20000 100000 10000 0 0 ecc efc ctl alu div top ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR Conventional 1D router Du+,SPIE'14 DSAR (a) Number of Vias (b) Wirelength 300 5000 250 4000 200 3000 150 2000 100 1000 50 0 0 ecc efc ctl alu div top ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR Conventional 1D router Du+,SPIE'14 DSAR (c) DSA conflicts (d) CPU(s) 33
Routing Result Routing Result Comparison Comparison 70000 600000 60000 1% better 1D router 1% overhead 1D router 500000 20% better SPIE’14 15% better SPIE’14 50000 400000 40000 300000 30000 200000 20000 100000 10000 0 0 ecc efc ctl alu div top ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR Conventional 1D router Du+,SPIE'14 DSAR (a) Number of Vias (b) Wirelength 300 5000 250 269 conflicts 1D router 4000 8 conflicts SPIE’14 200 3000 150 2000 100 1000 50 0 0 ecc efc ctl alu div top ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR Conventional 1D router Du+,SPIE'14 DSAR (c) DSA conflicts (d) CPU(s) 34
Routing Result Comparison Routing Result Comparison 70000 600000 60000 1% better 1D router 1% overhead 1D router 500000 20% better SPIE’14 15% better SPIE’14 50000 400000 40000 300000 30000 200000 20000 100000 10000 0 0 ecc efc ctl alu div top ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR Conventional 1D router Du+,SPIE'14 DSAR (a) Number of Vias (b) Wirelength 300 5000 250 269 conflicts 1D router 62% overhead 1D router 4000 8 conflicts SPIE’14 5% better SPIE’14 200 3000 150 2000 100 1000 50 0 0 ecc efc ctl alu div top ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR Conventional 1D router Du+,SPIE'14 DSAR (c) DSA conflicts (d) CPU(s) 35
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