UT DA DSAR: DSAR: DSA aware Routing with DSA aware Routing with - - PowerPoint PPT Presentation

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UT DA DSAR: DSAR: DSA aware Routing with DSA aware Routing with - - PowerPoint PPT Presentation

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UT DA DSAR: DSAR: DSA aware Routing with DSA aware Routing with Simultaneous DSA Guiding Simultaneous DSA Guiding Pattern and Double Patterning Pattern and Double Patterning Ass Assignment ignment Jiaojiao Ou 1 , Bei Yu 2 , Xiaoqing Xu 1

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UT DA

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DSAR: DSAR: DSA aware Routing with DSA aware Routing with Simultaneous DSA Guiding Simultaneous DSA Guiding Pattern and Double Patterning Pattern and Double Patterning Ass Assignment ignment

Jiaojiao Ou1, Bei Yu2, Xiaoqing Xu1, Joydeep Mitra3, Yibo Lin1, David Z. Pan1

1ECE Department, University of Texas at Austin 2CSE Department, CUHK 3Mentor Graphics Inc.

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Outline Outline

Introduction Problem formulation Detailed routing algorithms Experimental results Conclusion

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Intr Introduction:

  • duction: Technology

Technology Scaling Scaling

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AI / Cu / W wires Planar CMOS LE HNW VNW eNVM LELELE SADP SAQP

EUV LELE

10 nm 7 nm 5 nm 3 nm EUV EUV EBL

EUV DSA

Cu Doping 3D IC

Opto Connect Graphene CNT

FinFET LELE W LI Patterning Transistors

Complexity

Interconnect

2005 2010 2015 2020 2025

[Courtesy ARM]

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Technology Technology Scaling: M Scaling: More Mas

  • re Masks

ks

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Via Mask 1 Mask 2 Metal 3 Metal 2 Mask 3 Mask 4

Via density increases

 Triple/Quadruple patternings are required

  • Placement error problem
  • Cost increases

 More via: 1D design

(a) Original layout (b) Via layer with quadruple patterning

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Motivation Motivation of DSA

  • f DSA on Via
  • n Via Layer

Layer

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Reduce mask number by grouping vias in the same guiding pattern

Reduce 2 mask with DSA

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Consider Consider DSA DSA during Routing during Routing 1

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Initial detailed routing without DSA consideration

 3 masks are required

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Consider Consider DSA DSA during Routing during Routing 2

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Initial detailed routing without DSA consideration

 3 masks are required

Reroute n1 and n3

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Consider Consider DSA DSA during Routing during Routing 3

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Initial detailed routing without DSA consideration

 3 masks are required

Reroute n1 and n3

 Reduce 1 more mask

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Previous Previous Works Works

DSA-aware detailed routing for via layer

  • ptimization [Du+, SPIE’14]

 Resolve conflicts and infeasible via patterns during rip-up and reroute with negotiated congestion based scheme  Incapable to handle DSA with multiple patternings  More wire length may be introduced

Redundant Via insertion consideration [Lin+,

ASPDAC’17]

 Simultaneously consideration of redundant via insertion and guiding template feasibility  Increase redundant via insertion rate  Multiple patterning for via is not considered, not compatible for 1D design

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Problem Formulation: Problem Formulation: DSAR DSAR

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DSA and double patterning aware detailed routing

Input:

▷ Netlist with source/target pins ▷ Feasible DSA patterns ▷ Design rules

Output:

▷ Minimize wirelength, unroutable nets ▷ DSA-DP compatible via layer

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Forbidden Via distribution DSA design rules

Design Design Rules Rules

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Via

Cut mask

Metal 3 Metal 2

More complex guiding templates

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Pre Pre-rout route N e Net Planning et Planning - 1

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Construct conflict graph

 Vertices: bbox corners  Edge weight: DSA friendly? 1: 5

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Pre Pre-rout route N e Net Planning et Planning - 1

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Construct conflict graph

 Vertices: bbox corners  Edge weight: DSA friendly? 1: 5

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Pre Pre-rout route N e Net Planning et Planning - 1

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Construct conflict graph

 Vertices: bbox corners  Edge weight: DSA friendly? 1: 5

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Pre Pre-rout route N e Net Planning et Planning - 1

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Construct conflict graph

 Vertices: bbox corners  Edge weight: DSA friendly? 1: 5

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Pre Pre-rout route N e Net Planning et Planning - 1

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Construct conflict graph

 Vertices: bbox corners  Edge weight: DSA friendly? 1: 5

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Pre Pre-rout route N e Net Planning et Planning - 1

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Construct conflict graph

 Vertices: bbox corners  Edge weight: DSA friendly? 1: 5

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Pre Pre-rout route N e Net Planning et Planning - 1

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Construct conflict graph

 Vertices: bbox corners  Edge weight: DSA friendly? 1: 5

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Pre Pre-rout route N e Net Planning et Planning - 1

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Construct conflict graph

 Vertices: bbox corners  Edge weight: DSA friendly? 1: 5

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Pre Pre-rout route N e Net Planning et Planning - 2

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Conflict graph constraints

 At most 1 corner of each net

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Pre Pre-rout route N e Net Planning et Planning - 2

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Conflict graph constraints

 At most 1 corner of each net  Corners cross the pins of other nets

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Pre Pre-rout route N e Net Planning et Planning - 3

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Conflict graph constraints

 At most 1 corner of each net  Corners cross the pins of other nets

Conflict graph bipartization

 Pre-determine (estimate) the routing paths for nets

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Pre Pre-rout route N e Net Planning et Planning - 3

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Conflict graph constraints

 At most 1 corner of each net  Corners cross the pins of other nets

Conflict graph bipartization

 Pre-determine (estimate) the routing paths for nets  Minimize deleted vertices from conflict graph

  • DSA unfriendly vertices
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Pre Pre-rout route N e Net Planning et Planning - 4

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Net ordering for undetermined nets

 Smaller bbox (HPWL)  Overlaps

Route b first Route a first

More WL

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Detailed Detailed Routing Routing - 1

Routing graph model

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Routing box

Via inserted One color assignment forbidden All vias are forbidden

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Detailed Detailed Routing Routing - 2

Routing box state update

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Red via Green via All via forbidden grid Red via is forbidden Green via is forbidden Empty via M2 M3

Nearby routing box update Example

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Detailed Detailed Routing Routing - 3

Routing scheme

 Negotiated congestion based  A* search

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Detailed Detailed Routing Routing - 3

Routing scheme

 Negotiated congestion based  A* search

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Post Routing Post Routing Optimization Optimization

Assign DSA guiding patterns

 Minimize DSA groups and conflicts  Edge bipartization

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Post Routing Post Routing Optimization Optimization

Assign DSA guiding patterns

 Minimize DSA groups and conflicts  Edge bipartization

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Experimental Experimental Setup Setup

Implemented in C++ 3.4GHz Linux server, 32GB RAM ILP solver: GUROBI 6.5 OpenSparc T1 design:

 M2, M3 for routing  [Du+,SPIE’14], 1D router

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Routing Result Routing Result Comparison Comparison

10000 20000 30000 40000 50000 60000 70000 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

32 (a) Number of Vias

100000 200000 300000 400000 500000 600000 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

(b) Wirelength

50 100 150 200 250 300 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

(c) DSA conflicts

1000 2000 3000 4000 5000 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

(d) CPU(s) 1% better 1D router 20% better SPIE’14

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Routing Result Routing Result Comparison Comparison

10000 20000 30000 40000 50000 60000 70000 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

33 (a) Number of Vias

100000 200000 300000 400000 500000 600000 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

(b) Wirelength

50 100 150 200 250 300 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

(c) DSA conflicts

1000 2000 3000 4000 5000 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

(d) CPU(s) 1% better 1D router 20% better SPIE’14 1% overhead 1D router 15% better SPIE’14

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Routing Result Routing Result Comparison Comparison

10000 20000 30000 40000 50000 60000 70000 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

34 (a) Number of Vias

100000 200000 300000 400000 500000 600000 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

(b) Wirelength

50 100 150 200 250 300 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

(c) DSA conflicts

1000 2000 3000 4000 5000 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

(d) CPU(s) 1% better 1D router 20% better SPIE’14 1% overhead 1D router 15% better SPIE’14 269 conflicts 1D router 8 conflicts SPIE’14

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Routing Result Routing Result Comparison Comparison

10000 20000 30000 40000 50000 60000 70000 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

35 (a) Number of Vias

100000 200000 300000 400000 500000 600000 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

(b) Wirelength

50 100 150 200 250 300 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

(c) DSA conflicts

1000 2000 3000 4000 5000 ecc efc ctl alu div top Conventional 1D router Du+,SPIE'14 DSAR

(d) CPU(s) 1% better 1D router 20% better SPIE’14 1% overhead 1D router 15% better SPIE’14 269 conflicts 1D router 8 conflicts SPIE’14 62% overhead 1D router 5% better SPIE’14

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Comparison Comparison between W/ between W/ and WO and WO Net Net Planning Planning

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0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 ecc efc ctl alu div top w/ net planning wo net planning

(a) Number of Vias

0.9 0.95 1 1.05 1.1 1.15 ecc efc ctl alu div top w/ net planning wo net planning

(b) Wirelength

0.2 0.4 0.6 0.8 1 1.2 ecc efc ctl alu div top w/ net planning wo net planning

(c) CPU(s)

With v.s. without net planning

▷ 19% less via number ▷ 8% less wirelength ▷ 7% more runtime

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Conclusion Conclusion

DSA and double patterning for via layer in detailed routing

 Pre-route net planning  Routing model with DSA-DP consideration  Post-routing optimization to improve DSA guiding pattern assignment and decomposition

Future work

 Adaptive to more routing layers  General to more DSA and multiple patterning considerations

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TH THANK ANK YOU YOU

Q&A

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