Delay Test Virendra Singh Associate Professor C omputer A - - PowerPoint PPT Presentation

CADSL

Delay Test

Virendra Singh

Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay

http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in

EE-709: Testing & Verification of VLSI Circuits

Lecture 27 (26 March 2013)

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Definitions

Controlling value (cv) : An input of a gate is said to have a controlling value if it uniquely determines the output of the gate independent of other inputs

• For example, 0 for AND or NAND

A path R in a circuit is a sequence (g0g1……gr), where g0 is a PI, g1g2.. are gate outputs, gr is a PO

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Definitions

An on-input of path R is a connection between two gates along path R A side-input (off-input) of path R is any connection to a gate along path R other than its on-input A path that starts at a primary input and ends at a side-input of path R is called a side-path

• f R

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Transition Delay Fault

• Two faults per gate; slow-to-rise and

slow-to-fall.

• Tests are similar to stuck-at fault tests.

For example, a line is initialized to 0 and then tested for s-a-0 fault to detect slow-to-rise transition fault.

• Models spot (or gross) delay defects.

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Transition Delay Test

1 3 1 1 1 2 Path P1 P2 P3 SA0 D D D D’ 1 D 1

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Transition Delay Test

1 3 1 1 1 2 Path P1 P2 P3

Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew

SA0 D D D D’ D’

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Transition Delay Test

1 3 1 01 01 2 Path P1 P2 P3 SA0 0D 0D 0D 1D’ 00 X0 1D’

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Path Delay Fault Cheng’s classification

• Robustly testable
• Non-robustly (NR) testable
• Functional sensitizable (FS) testable
• Functionally unsensitizable (functionally

redundant)

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Path Delay Fault

Robust testable : detect target PDF independent of delays in rest of the circuit. It must satisfies the following conditions

• It launches the desired transition at primary

input

• All side inputs of target path settle to non-

controlling values under V2

• Whenever the logic transition at an on-input

is from non-controlling to controlling value (ncv to cv), each side-input should maintain steady non-controlling value (ncv)

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Path Delay Fault

Robust testable

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Path Delay Fault

Non-Robust (NR ) testable :

It must satisfies the following conditions

• It launches the desired transition at primary

input

• All side-inputs of target path settle to non-

controlling values (ncv) under V2

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Path Delay Fault

Functional Sensitizable (FS) testable:

 Detection of faults on paths that are sensitizable

under FS criterion depends on the delays on signals outside the target path

 It must satisfies the following conditions

• It launches the desired transition at primary

input

• Whenever the logic transition at an on-input

is non-controlling value (ncv) under vector V2, each side-input should have non- controlling value (ncv) under V2