Low Cost Launch- -on on- -Shift Shift Low Cost Launch Delay - - PowerPoint PPT Presentation

SLIDE 1

Low Cost Launch Low Cost Launch-

• on
• n-
• Shift

Shift Delay Test with Slow Scan Delay Test with Slow Scan Enable Enable (ETS06)

(ETS06)

Gefu Gefu Xu Xu Adit Adit D. Singh

• D. Singh

Auburn University Auburn University

SLIDE 2

Outline Outline

• Transition Delay Test (Launch

Transition Delay Test (Launch-

• on
• n-
• Shift, Launch

Shift, Launch-

• on
• n-
• Capture)

Capture)

• The issue of LOS: requiring fast scan enable signals

The issue of LOS: requiring fast scan enable signals

• Current approach I: Pipeline structure methods

Current approach I: Pipeline structure methods

• Current approach II: Partial

Current approach II: Partial-

• shift

shift-

• partial

partial-

• capture

capture methods methods

• Other approaches: Hybrid method and Enhanced Scan

Other approaches: Hybrid method and Enhanced Scan method method

• Our solution: Using Delay Test Scan Flip

Our solution: Using Delay Test Scan Flip-

• flops with slow

flops with slow scan enable signals scan enable signals

SLIDE 3

Transition Delay Test Transition Delay Test

Delay Test

Functional Test Structure Test Speed Binning Transition Delay Test Path Delay Test Launch-On-Shift LOS Launch-On-Capture LOC

Figure 1: Classification of Delay Test

SLIDE 4

LOS & LOC Delay Test LOS & LOC Delay Test

Figure 2: Overview of scan based delay testing Figure 3: Multiplexer based scan flip-flop Figure 4: Waveforms for LOS and LOC delay test

SLIDE 5

LOS & LOC Delay Test LOS & LOC Delay Test

1)Medium fault coverage 2) More test patterns 3)Sequential ATPG 1) Requiring fast scan enable signals Disadvantage 1) No requirement for fast scan enable signals 1)High fault coverage 2)Few test patterns 3)Combination ATPG Advantage Launch-on-Capture (LOC) Launch-on-Shift (LOS)

Table1: Comparison of LOS & LOC

SLIDE 6

Issue of LOS: Requiring Fast Scan Issue of LOS: Requiring Fast Scan Enable Signals Enable Signals

• DFT design cost

DFT design cost

High speed global scan enable signal High speed global scan enable signal -

• > routing the

> routing the scan enable signal as clock signal scan enable signal as clock signal -

• > DFT design cost is

> DFT design cost is expensive expensive

• Hard to meet time closure

Hard to meet time closure

“ “From our experience, the design effort involved in From our experience, the design effort involved in designing a fast SEN signal and the resulting impact on designing a fast SEN signal and the resulting impact on turnaround time is considered unacceptable for many turnaround time is considered unacceptable for many

• designs. We believe that this concern is shared by others
• designs. We believe that this concern is shared by others

in the design and test community. in the design and test community.” ” (ref.[8]) (ref.[8])

SLIDE 7

Approach I: Pipeline structure Approach I: Pipeline structure methods methods

Figure5: Test architecture Figure 6: Last transition generator (LTG) cell

SLIDE 8

• The values in LTG cell

The values in LTG cell determine the test determine the test mode (LOS or LOC). mode (LOS or LOC).

• Both LOS and LOC test

Both LOS and LOC test are allowed. are allowed.

• Local fast scan enable

Local fast scan enable signals are needed and signals are needed and drivability requirements drivability requirements for these signals are for these signals are considerable. considerable.

• Timing critical signals

Timing critical signals (enable signals) (enable signals) complicate layout and complicate layout and timing closure. timing closure.

Figure 7: Operation of LTG cell, (b) LOS and (c) LOC

1

100

1000[10]1110

SLIDE 9

Approach II: Partial Approach II: Partial-

• shift

shift-

• partial

partial-

• capture methods

capture methods

Figure 8: Modified Local scan enable generator (LSEG) cell Figure 9: Test Structure

SLIDE 10

• The value in LSEG

The value in LSEG determines the mode determines the mode (LOC or enhanced (LOC or enhanced LOC). LOC).

• LOC and enhanced

LOC and enhanced LOC mode which LOC mode which restricts a subset of restricts a subset of scan chain only scan chain only

• perating in shift mode
• perating in shift mode

are allowed. are allowed.

• Fault coverage is only

Fault coverage is only a little higher than a little higher than pure LOC pure LOC

• Timing critical signals

Timing critical signals (enable signals) (enable signals) complicate layout and complicate layout and timing closure. timing closure.

Figure 10: Operation of LSEG cell (a) Scan chain (b) Conventional LOC and (c) Enhanced LOC

SLIDE 11

Other approaches: Hybrid method Other approaches: Hybrid method

• Using a slow scan enable signal to generate a

Using a slow scan enable signal to generate a fast scan enable signal fast scan enable signal

• Some Scan Flip

Some Scan Flip-

• flops are controlled by Slow

flops are controlled by Slow Scan Enable signal and other Scan Flip Scan Enable signal and other Scan Flip-

• flops

flops (few) are controlled by Fast Scan Enable signal. (few) are controlled by Fast Scan Enable signal.

Figure 11: Fast Scan Enable Signal Generator

SLIDE 12

Other approaches: Enhanced Scan Other approaches: Enhanced Scan method method

Figure 12: Dual Flip-flop Table 2: Dual Flip-flop operation

• Double all scan Flip

Double all scan Flip-

• flops to allow LOS and LOC

flops to allow LOS and LOC

• If partial scan Flip

If partial scan Flip-

• flops are doubled, it works as

flops are doubled, it works as Partial Partial-

• shift

shift-

• partial

partial-

• capture mode

capture mode

SLIDE 13

Contribution of this paper Contribution of this paper

• Designed a new structure

Designed a new structure --

• - Delay Test

Delay Test Scan Flip Scan Flip-

• flop (DTSFF) to support LOS

flop (DTSFF) to support LOS transition delay testing transition delay testing

• Designed modified DTSFF (type I) to

Designed modified DTSFF (type I) to support both LOS and LOC delay testing support both LOS and LOC delay testing

• Designed modified DTSFF (type II) to

Designed modified DTSFF (type II) to support mixed LOS and LOC delay testing support mixed LOS and LOC delay testing (even higher fault coverage) (even higher fault coverage)

SLIDE 14

Experiment results Experiment results

50 55 60 65 70 75 80 85 90 95 100 S 2 8 S 2 9 8 S 3 4 4 S 3 4 9 S 3 8 2 S 3 8 6 S 4 S 4 2 S 4 4 4 S 5 1 S 5 2 6 S 5 2 6 n S 6 4 1 S 7 1 3 S 8 2 S 8 3 2 S 9 5 3 S 1 1 9 6 S 1 2 3 8 S 1 4 2 3 S 1 4 8 8 S 1 4 9 4 S 5 3 7 8 S 9 2 3 4 S 1 3 2 7 S 1 5 8 5 A v e r a g e ISCAS89 Fault Coverage

LOC (100k) LOS (100k) LOS+LOC (200k) MIX (200k)

SLIDE 15

Conclusion Conclusion

• Basic DTSFF allows LOS test with slow scan

Basic DTSFF allows LOS test with slow scan enable signal enable signal

• Modified DTSFF (type I & II) allow LOS+ LOC

Modified DTSFF (type I & II) allow LOS+ LOC test and Mix LOS/LOC test test and Mix LOS/LOC test

• The overhead for DTSFF is small.

The overhead for DTSFF is small.

• The Fault coverage for DTSFF design is high.

The Fault coverage for DTSFF design is high.

• DTSFF is compatible with current EDA tools and

DTSFF is compatible with current EDA tools and design flows. design flows.

SLIDE 16

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SLIDE 17

Thank you! Thank you!