Delay Test Virendra Singh Associate Professor C omputer A - - PowerPoint PPT Presentation

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Delay Test Virendra Singh Associate Professor C omputer A rchitecture and D ependable S ystems L ab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in

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Delay Test

Virendra Singh

Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay

http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in

EE-709: Testing & Verification of VLSI Circuits

Lecture 28 (28 March 2013)

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Path Delay Fault Cheng’s classification

Robustly testable
Non-robustly (NR) testable
Functional sensitizable (FS) testable
Functionally unsensitizable (functionally

redundant)

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Path Delay Fault

Robust testable : detect target PDF independent of delays in rest of the circuit. It must satisfies the following conditions

It launches the desired transition at primary

input

All side inputs of target path settle to non-

controlling values under V2

Whenever the logic transition at an on-input

is from non-controlling to controlling value (ncv to cv), each side-input should maintain steady non-controlling value (ncv)

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Path Delay Fault

Robust testable

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Path Delay Fault

Non-Robust (NR ) testable :

It must satisfies the following conditions

It launches the desired transition at primary

input

All side-inputs of target path settle to non-

controlling values (ncv) under V2

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Path Delay Fault

Functional Sensitizable (FS) testable:

 Detection of faults on paths that are sensitizable

under FS criterion depends on the delays on signals outside the target path

 It must satisfies the following conditions

It launches the desired transition at primary

input

Whenever the logic transition at an on-input

is non-controlling value (ncv) under vector V2, each side-input should have non- controlling value (ncv) under V2

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Path Delay Fault

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Path Delay Fault

Functionally unsensitizable

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Path Delay Fault

On-input Side-inputs Testability cv -> ncv Stable cv Untestable Stable ncv Robust cv -> ncv ncv -> cv Untestable ncv -> cv Stable cv Untestable Stable ncv Robust cv -> ncv NR ncv -> cv FS

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Robust Test Conditions

 Real events on target path.  Controlling events via target path.

V1 V2 V1 V2 V1 V2 V1 V2 V1 V2 V1 V2 U1 U1 U1/R1 S1 U0/F0 S1 U0 U0 U0/F0 U1/R1 U1/R1 U1/R1 U0/F0 U0/F0 S0 S0

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A Five-Valued Algebra

 Signal States: S0, U0 (F0), S1, U1 (R1), XX.  On-path signals: F0 and R1.  Off-path signals: F0=U0 and R1=U1.

S0 U0 S1 U1 XX S0 S0 S0 S0 S0 S0 U0 S0 U0 U0 U0 U0 S1 S0 U0 S1 U1 XX U1 S0 U0 U1 U1 XX XX S0 U0 XX XX XX Input 1 Input 2 S0 U0 S1 U1 XX S0 S0 U0 S1 U1 XX U0 U0 U0 S1 U1 XX S1 S1 S1 S1 S1 S1 U1 U1 U1 S1 U1 U1 XX XX XX S1 U1 XX Input 1 Input 2 Input S0 U0 S1 U1 XX S1 U1 S0 U0 XX AND OR NOT Ref.: Lin-Reddy IEEETCAD-87

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Robust Test Generation

R1 S0 U0 R1 XX S0 U0 F0 U0 Path P3 Test for P3 – falling transition through path P3: Steps A through E F0 XX

A. Place F0 at

path origin

B. Propagate F0 through OR gate;

also propagates as R1 through NOT gate

C. F0 interpreted as U0;

propagates through AND gate

D. Change off-path input

to S0 to Propagate R1 through OR gate

E. Set input of AND gate to

S0 to justify S0 at output Robust Test: S0, F0, U0

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Non-Robust Test Generation

U1 U0 XX U1 U0 R1 R1 Path P2 Fault P2 – rising transition through path P2 has no robust test. R1 XX

A. Place R1 at

path origin

B. Propagate R1 through OR gate;

interpreted as U1 on off-path signal; propagates as U0 through NOT gate

D. R1 non-robustly propagates

through OR gate since off- path input is not S0

C. Set input of AND gate to

propagate R1 to output Non-robust test: U1, R1, U0 U1 Non-robust test requires Static sensitization: S0=U0, S1=U1 R1

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Functional Sensitizable TG

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FS Untestable Faults

S1 U1 XX S1 U0 F0 F0 Path P2 Fault P2 – falling transition through path P2 has no test. F0 XX

A. Place R1 at

path origin

B. Propagate R1 through OR gate;

interpreted as U1 on off-path signal; propagates as U0 through NOT gate

D. F0 cannot be propagated

through OR gate since off- path input is not S0

C. Set input of AND gate to

propagate F0 to output Non-robust test: U1, R1, U0 U0 NO TEST F0

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Slow-Clock Test

Input test clock Output test clock Combinational circuit Input latches Output latches

Input test clock Output test clock

V1 applied V2 applied Output latched

Test clock period Rated clock period

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Enhanced-Scan Test

Combinational circuit HL SFF HL SFF PI PO SCANIN SCAN- OUT HOLD CK TC CK TC CK: system clock TC: test control HOLD: hold signal SFF: scan flip-flop HL: hold latch CK HOLD CK period

Normal mode Normal mode

TC Scan mode V1 PI applied V2 PI applied Scanin V1 states Scanin V2 states V1 settles Result latched Scanout result

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Normal-Scan Test

Combinational circuit SFF SFF PI PO SCANIN SCAN- OUT CK TC CK TC CK: system clock TC: test control SFF: scan flip-flop

Rated CK period

Normal mode

TC (A)

Scan mode V1 PIs applied V2 PIs applied

Scanin V1 states Result latched Result scanout V2 states generated, (A) by one-bit scan shift of V1, or (B) by V1 applied in functional mode.

Scan mode Normal mode

TC (B)

Scan mode Scan mode Slow CK period

Gen. V2

states

Path tested

Slow clock