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Welcome Arch vs arch Microcode Lab 1 Overview CS152: Discussion Section 1 Introduction / Microprogramming / Lab 1 Overview Albert Ou, Yue Dai Department of Electrical Engineering and Computer Sciences University of California, Berkeley

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Welcome Arch vs µarch Microcode Lab 1 Overview

CS152: Discussion Section 1

Introduction / Microprogramming / Lab 1 Overview Albert Ou, Yue Dai

Department of Electrical Engineering and Computer Sciences University of California, Berkeley

January 31, 2020

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Welcome

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Meet your GSIs

Albert Ou

  • Email: aou@eecs.berkeley.edu
  • Office Hours: Monday 3pm-4pm, 326 Soda Hall
  • PhD student (advised by Krste Asanovi´

c)

  • Research focus: Vector architectures, data-parallel accelerators
  • CS152 survivor from long ago (2012)

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Meet your GSIs

Yue Dai

  • Email: yuedai96@berkeley.edu
  • Office Hours: Tuesday 4:30pm-5:30pm, 347 Soda Hall
  • PhD student (advised by Borivoje Nikoli´

c)

  • Research focus: Massive MIMO transceiver baseband system (6+G)

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Agenda

1 Architecture vs microarchitecture 2 Microcoding review 3 Lab 1 overview

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Administrivia

  • Problem Set 1 due at 10:30am Mon, Feb 10
  • Lab 1 due at 10:30am Wed, Feb 19
  • Submit assignments through Gradescope
  • https://www.gradescope.com/courses/84575
  • Join with code 9VZ526
  • Check course webpage for schedule
  • http://www-inst.eecs.berkeley.edu/~cs152/sp20/
  • Sign up for Piazza
  • http://piazza.com/berkeley/spring2020/cs152

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Arch vs µarch

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What is an ISA?

“The term architecture is used here to describe the attributes of a system as seen by the programmer, i.e., the conceptual structure and functional behavior, as distinct from the organization of the data flow and control, the logic design, and the physical implementation.”

  • G. M. Amdahl, G. A. Blaauw, and F. P. Brooks, “Architecture of the IBM system/360,”

IBM Journal of Research and Development, vol. 8, no. 2, pp. 87–101, Apr. 1964

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Architecture vs Microarchitecture

Architecture: the instruction set Q: What are some examples of ISAs? (What might you find in a server? In a mobile device?) Microarchitecture: the implementation (organization) of an architecture Q: Is it necessarily hardware? Q: What might be the fastest RISC-V implementation publically available?

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What does it mean to be architecturally visible?

Instructions perform operations on architecturally visible state to do useful work. Q: Is the following exposed by the architecture (true/false)?

1 Register file entries in a classical RISC

pipeline

2 The stack in a stack architecture 3 Pipeline registers 4 Branch-delay/load-delay slots 5 NOPs 6 Pipeline bubbles 7 Condition code/flags 8 Memory address width 9 Instruction/data caches

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Classifying ISAs based on addressing modes

(Computer Architec- ture, A Quantitative Approach: Appendix A)

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Power of Abstraction

ISA – “most important interface in computer system”

  • Where hardware meets software
  • Simple does not necessarily mean less functional
  • Just 101 RISC-V instructions are sufficient to run a full OS (GNU/Linux) and

applications!

  • User-level: RV64I (40+15) + M (8+5) + A (11+11)
  • Privileged: Sv39 (7+4)
  • Optional: F (26+4) + D (26+6) + C (45)

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Power of Abstraction

How to bootstrap a new ISA

  • How many lines of code (C, assembly) needed to port a kernel and toolchain?

Linux : 113 files changed, 10307 insertions(+), 1 deletion(-) gcc : 67 files changed, 10295 insertions(+), 11 deletions(-) binutils : 56 files changed, 9982 insertions(+), 20 deletions(-) glibc : 178 files changed, 15169 insertions(+), 5 deletions(-)

  • ∼ 90% of Debian packages built for RV64 (Q2 2019; “buster”)
  • Out of 25,283 source packages
  • Out of 1,018,427,218 source lines of code

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So easy a dozen grad students can do it!

  • EOS22 tape-out (2014)
  • IBM 45nm SOI process
  • 1.65 GHz core frequency
  • 1st or 2nd RISC-V chip

to boot Linux

  • C. Sun, M. T. Wade,
  • Y. Lee, et al., “Single-chip

microprocessor that communicates directly using light,” Nature, vol. 528, p. 534, Dec. 2015

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Microcode

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Microprogramming

  • Separation of datapath (arithmetic, data movement) from control (sequencing of
  • perations on datapath)
  • Microcode program is essentially a description of a finite state machine
  • Implements an “interpreter” for a software-visible ISA (e.g., RISC-V)
  • Each microinstruction corresponds to one “state”
  • Microinstruction specifies outputs for given state and the next state

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Single-Bus Datapath

IR A B RegWr enReg MemWr enMem MA

addr addr data data

rs2 rs1 1 rd 32(PC) 1(RA)

RegSel busy? zero? ALUOp Opcode ldIR ldA ldB ldMA IntRq Memory 32 GPRs + PC

(32-bit registers)

ALU enALU

Immed Select

enImm ImmSel Bus

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Microcoded vs Pipelined

Q: How does a microcoded implementation differ from a classical RISC pipeline? Consider how the various instruction execution phases are implemented:

  • Instruction fetch
  • Instruction decode
  • Register read
  • ALU operations
  • Optional memory operations
  • Optional register writeback
  • Next instruction address (PC) calculation

Q: Why does microcoding generally facilitate a simpler microarchitecture?

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Historical Context

Q: Why did microcoding make sense historically?

  • ROM was cheaper and faster than logic
  • Simplified control complexity (helps verification)
  • CISC yielded better code density

(Do these still hold true today?)

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Historical Context

Recurring theme in architecture:

  • Design choices are influenced by the limitations of available circuit technology
  • Re-evaluation becomes necessary as technology changes

Avoid repeating past mistakes. . . but also know when old lessons may not apply

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Preemptive Clarification

Note: MemEn and RegEn are treated differently in the lecture and handout

Lecture Handout

Main Memory PC Registers 32 (PC) rd rs1 rs2 Register RAM Address In Data Out

  • Mem. Address

RegEn MemEn MemW RegW MALd RegSel Busy? Register RAM Main Memory RegEn RegW RegSel rs1 rs2 rd 32(PC) 1 (ra) MA MemEn MALd Busy? MemW

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Preemptive Clarification

RAM Array

Write/Read we ChipEnable addr dout din bus (internal details from handout)

MemEn and RegEn semantics

Lecture : Enable for tri-state buffer only Handout : General “chip enable” (CE)

  • Must also be asserted for writes,

not only reads

  • Nothing happens with memory

if de-asserted (logical 0)

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Preemptive Clarification

Tri-state buffers versus multiplexors

encoder

Bus using N tri-state buffers Bus using N:1 mux tree

  • Microcoded implementation in Lab 1 (Sodor) uses a mux tree instead of tri-state

buffers to drive the bus

  • Functionally equivalent; friendlier to logic synthesis
  • Easier mapping to ASIC standard cells and FPGA CLBs
  • Design simplicity is worth the marginal area overhead

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Preemptive Clarification

Takeaways

  • We will adhere to the lecture’s convention for convenience
  • Handout will be eventually updated to match
  • Will be clarified in exam questions
  • Many approaches are valid depending on implementation style
  • Be aware that old exam/quiz solutions may use differing conventions
  • When in doubt, state your assumptions clearly in answers

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Lab 1 Overview

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Lab Logistics

  • CS152 is partitioned into 5 modules
  • 1 problem set per module (∼ 1.5 weeks to complete)
  • 1 lab per module (∼ 2.5 weeks to complete)
  • Labs are “take-home” assignments
  • No dedicated lab sessions
  • Lab infrastructure pre-installed on instructional Linux servers
  • Log in remotely through ssh
  • Request an EECS instructional user account:

(Log into WebAcct service with CalNet ID) https://acropolis.cs.berkeley.edu/~account/webacct/

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Lab Reports

Lab reports must be typed in readable English – no raw dumps!

  • Directed portion
  • Must be completed individually
  • Submit one report per person on Gradescope
  • Open-ended portion
  • Pick one problem to do
  • Feel free to collaborate in groups of 2 or 3
  • Submit one report per group on Gradescope (limit 6 pages)
  • Feedback
  • Write as much or as little as desired – marked down only if completely omitted
  • Please answer team feedback questions
  • Append feedback to individual report

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Lab 1

Due on Feb 19 – start early!

  • Gentler introduction to simulation flow and software toolchain
  • Given source code for processor design descriptions
  • Build cycle-accurate simulators
  • Run benchmarks in behavioral RTL-level simulation; gather data
  • CPI
  • Instruction mix
  • Analyze; make recommendations; propose new designs

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Lab Framework

  • CS152 labs are built on current research infrastructure (designs, tools, flows)
  • Developed from scratch at UC Berkeley over past 10 years
  • We will strive to use real hardware implementations wherever possible
  • More interesting than a contrived pure-software model
  • Enables more realistic experiments
  • Actual systems sometimes exhibit counter-intuitive behavior

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Chisel

  • New hardware description language from

UC Berkeley

  • Embedded in Scala
  • A Chisel design is a legal Scala program that

produces a digital logical circuit as a graph data structure (FIRRTL)

  • Elaborates into synthesizable Verilog RTL
  • Leverage object-oriented/functional

programming paradigms to write highly parameterized generators

  • Industry adoption: SiFive, Google, others

https://www.chisel-lang.org/

Chisel language frontend FIRRTL passes Chisel design (*.scala) GDSII layout + netlist manipulation + dead code elimination + statistics collection Verilog for SW sim Verilog for FPGA Verilog for ASIC Verilator compilation FPGA syn/ place/route VLSI syn/ place/route Hardware compiler framework FPGA bitstream Cycle-accurate C++ model CS152 Section 1 2020-01-31 30 / 32

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Chisel

NOTE: Students will NOT be required to implement hardware in Chisel!

  • Complete processor designs in Chisel will be

provided to you in labs

  • But will need to know how to configure

parameters to generate different designs

  • Can choose to write Chisel RTL for some
  • pen-ended problems

Chisel language frontend FIRRTL passes Chisel design (*.scala) GDSII layout + netlist manipulation + dead code elimination + statistics collection Verilog for SW sim Verilog for FPGA Verilog for ASIC Verilator compilation FPGA syn/ place/route VLSI syn/ place/route Hardware compiler framework FPGA bitstream Cycle-accurate C++ model CS152 Section 1 2020-01-31 31 / 32

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Sodor

  • Collection of basic RV32I processors

implemented in Chisel

  • 1-stage pipeline
  • 2-stage pipeline
  • 3-stage pipeline
  • 5-stage pipeline
  • Fully bypassed
  • Interlocked (all hazards resolved

by stalling)

  • Microcoded
  • Educational: Favors clarity and

simplicity over PPA optimizations (power/performance/area)

Top Tile

Core CtlPath DatPath 3-ported Main Memory Debug Module Debug Module Interface

Test Harness

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