CRC enter for eliable omputing Application-Dependent Testing of - - PowerPoint PPT Presentation

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Application-Dependent Testing of FPGAs

Mehdi Baradaran Tahoori PhD Candidate, Stanford CRC

MSEE’02 Stanford, BSCE’00 Sharif Research Interests: FPGA Testing, Reliability in DSM VLSI

enter for eliable

• mputing

CRC

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Background

Problem Statement Test routing resources used in a mapped Design Motivation Mapped designs not fully testable Applications Application-Specific FPGA System-level Testing

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Approach

Implement testable functions in logic blocks Configuration of routing resources unchanged Advantages ◆ No extra place-and-route for test configurations ◆ Fast reconfiguration time ◆ Configuration storage overhead minimized ◆ No fault missed due to partitioning ◆ Works for all SRAM-based FPGAs and CPLDs

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Basic Idea

Single-term functions Logic function with only one minterm or maxterm Activating Input input values for single minterm (maxterm) ✪

All sensitized faults are detectable

Test vector = activating input A1, B0 , C1, D1, F0, ABFB, BBFC, BBFD D C B A

F F = A′BC′D′

&

1 1

B stuck-at 0 Bridging between B and D

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& & +

Entire FPGA

Single-term functions in all used logic cells Inputs of each logic cell = activating input Sequential Designs Preset flip-flops Number of test cycles = Max sequential depth

Longest sequential path from PI to PO

1 1 1 1

preset to 0 preset to 1

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Test Configuration Generation

Which single-term functions? Depend on fault list

Transition faults : all-AND, all-OR

Robust transition fault testing

Bridging faults Other…

D C B A

F

1 1 F (F′) = A′ B′CD

D C B A

F

1 1 F (F′) = A′ BC′D

{(ABFC),(ABFD),(BBFC),(BBFD)} {(ABFB),(ABFD),(BBFC),(CBFD)}