Carbon Nanotube Imperfection-Immune Digital VLSI Subhasish Mitra - PowerPoint PPT Presentation

Carbon Nanotube Imperfection-Immune Digital VLSI Subhasish Mitra Robust Systems Group Department of EE & Department of CS Stanford University H. Chen, J. Deng, A. Hazeghi, A. Lin, N. Patil, M. Shulaker, L. Wei, H. Wei, Prof. H.-S. P. Wong, J. Zhang

Carbon Nanotube FET (CNFET) D Carbon Nanotube (CNT) Diameter (D) : 0.5 - 3 nm S. Iijima 2

Ideal CNFET Inverter P+ doped Vdd Semiconducting Lithographic CNTs pitch Input 4nm Sub-lithographic Output Gates pitch N+ doped Semiconducting Gnd CNTs 3

CNFET Technology Milestones 1998 1998 2004 2004 First CNFET First CNFET Best single-CNT Best single-CNT demonstration demonstration CNFET CNFET [Delft, IBM] [Delft, IBM] [Stanford] [Stanford] 2001 2001 2006 2006 Single-CNT Single-CNT Single-CNT Single-CNT logic gates logic gates ring osc. ring osc. [IBM] [IBM] [IBM] [IBM] 4

CNFETs: BIG Promise, BUT � Major barriers for a decade � Mis-positioned nanotubes � Metallic nanotubes � Processing alone inadequate Imperfection-immune design essential 5

Mis-positioned CNTs � � Incorrect Logic � � Vdd A B C D Out A C Wanted: A ′ C ′ + B ′ D ′ Got: A ′ C ′ + B ′ D ′ + A ′ D ′ D B Wanted: (A+C) (B+D) Gnd Got : B+D 6

Metallic CNTs Semiconducting CNT (s-CNT) Metallic CNT (m-CNT) CNFET with s-CNT CNFET with m-CNT Current Current Transistor No gate control V g V g Typical: 10 – 50% grown CNTs metallic 7

Results � Yesterday � SSI single-CNT ring oscillator � Today � Imperfection-immune VLSI circuits 8

CNFET Technology Milestones 2008 2009 2009 Mis-positioned- Imperfection- Monolithic 1998 2004 2004 First CNFET Best single-CNT Best single-CNT CNT-immune immune adders 3D CNT demonstration CNFET CNFET VLSI logic gates & latches circuits [Delft, IBM] [Stanford] [Stanford] [Stanford] [Stanford] [Stanford] 2001 2001 2006 2006 2008 2009 2010 Single-CNT Single-CNT Single-CNT Single-CNT Flexible Defect- Ultra-short logic gates logic gates ring osc. ring osc. CNT tolerant channel [IBM] [IBM] [IBM] [IBM] circuits logic gates CNFETs [UIUC] [USC] [IBM] 9

CNFET Technology Outlook Problem Challenge Status CNT alignment Correct function & positioning Correct function Metallic CNT Low leakage High current CNT density density Complementary CNT doping CNFETs 10

Outline � Introduction � Mis-positioned-CNT-immune logic � Metallic-CNT-immune logic � CNT variations � Conclusion Patil, IEEE TCAD 2008, Symp. VLSI Tech. 2008 11

Mis-positioned-CNT-Immune NAND 1. Grow CNTs 12

Mis-positioned-CNT-Immune NAND Vdd 1. Grow CNTs 2. Extended gate & contacts A B Out CRUCIAL A B Gnd 13

Mis-positioned-CNT-Immune NAND Vdd 1. Grow CNTs 2. Extended gate & contacts A B 3. Etch gate & CNTs Out 4. Chemically dope P & N regions A B Gnd 14

Mis-positioned-CNT-Immune NAND Vdd 1. Grow CNTs 2. Extended gate & contacts A B 3. Etch gate & CNTs Etched Out region 4. Chemically dope P & N regions ESSENTIAL A B � Graph algorithms � All possible functions Gnd 15

Automated Algorithms � Given: Layout � Determine • Mis-positioned-CNT immune ? 16

Mis-positioned-CNT-Immune NAND Contact Contact Doped A B GB GA E Doped Contact Contact 1 Contact Intended: A or B 1 Doped A B 0 Etched Gate A Gate B 1 Doped 1 Contact 17

Mis-positioned-CNT-Immune NAND C-D-A-D-C : A Contact Contact Doped A B GB GA E Doped Contact Contact 1 Contact Intended: A or B 1 Doped A B 0 Etched Gate A Gate B 1 Doped 1 Contact 18

Mis-positioned-CNT-Immune NAND C-D-A-D-C : A Contact Contact C-D-B-D-C : B Doped A B GB GA E Doped Contact Contact 1 Contact Intended: A or B 1 Doped A B 0 Etched Gate A Gate B 1 Doped 1 Contact 19

Mis-positioned-CNT-Immune NAND C-D-A-D-C : A Contact Contact C-D-B-D-C : B Doped C-D-B-D-A-D-B-D-C : A & B A B GB GA E Doped Contact Contact 1 Contact Intended: A or B 1 Doped A B 0 Etched Gate A Gate B 1 Doped 1 Contact 20

Mis-positioned-CNT-Immune NAND C-D-A-D-C : A Contact Contact C-D-B-D-C : B Doped C-D-B-D-A-D-B-D-C : A & B A B C-D-E-D-C : 0 GB GA E … Doped Contact Contact 1 Contact Intended: A or B 1 Doped A B 0 Etched Gate A Gate B 1 Doped 1 Contact 21

Mis-positioned-CNT-Immune NAND C-D-A-D-C : A Contact Contact C-D-B-D-C : B Doped C-D-B-D-A-D-B-D-C : A & B A B C-D-E-D-C : 0 GB GA E … Doped Contact Contact 1 Contact Intended: A or B 1 Doped A Implemented: B 0 A or B or Etched Gate A Gate B (A & B) or 0 == 1 Doped A or B 1 Contact 22

Automated Algorithms � Given: Logic function � Produce • Mis-positioned-CNT immune layout 23

Mis-positioned-CNT-Immune Layout Vdd / Gnd Contact Etched regions CNTs B C A Gates Intermediate Contact D E Out = Output Contact A + (B + C)(D + E) � Immune to LARGE number of mis-positioned CNTs � Efficient 24

Most Importantly � VLSI processing � No die-specific customization � VLSI design flow � Immune library cells 25

CNT Growth on Silicon Substrates � Highly mis-positioned � Not desirable for VLSI 4 µm 10 µm 26

First Wafer-Scale Aligned CNT Growth Quartz wafer with catalyst Aligned CNT growth SEM image (grown CNTs) Quartz wafer 99.5% CNTs aligned 27

Wafer-Scale CNT Transfer � Silicon substrates for VLSI � Low temperature (90 o C – 120 o C) processing Thermal Release Adhesive Tape Before transfer After transfer Source Substrate (Quartz) Target Substrate (SiO 2 /Si) 2 µm 2 µm 28

First VLSI Demonstration Mis-positioned-CNT-immune logic gates NAND, NOR, AND-OR-INV, OR-AND-INV Etched Region 10µm 10µm 10µm NAND pullup NOR pullup ��� ��� ������������� ������������� �� ���� � � � ��� ��� �� �� � ��� ��� �� �� � ��� �� ��� �� � ��� �� ��� �� ������������������� ������������������� 29

Outline � Introduction � Mis-positioned-CNT-immune logic � Metallic-CNT-immune logic � CNT variations � Conclusion Patil, IEDM 2009, Shulaker, Nanoletters 2011, Wei, IEDM 2009, Symp. VLSI Tech. 2010 30

Metallic CNTs Semiconducting CNT (s-CNT) Metallic CNT (m-CNT) CNFET with s-CNT CNFET with m-CNT Current Current Transistor No gate control V g V g Typical: 10 – 50% grown CNTs metallic 31

m-CNT Processing Options � Grow 0% m-CNTs � Open challenge � Remove m-CNTs after growth � 99.99% removal required 32

Existing m-CNT Removal � Sort CNTs � Inadequate � SDB � S ingle D evice electrical B reakdown � Not scalable 33

SDB Technique � Current-induced m-CNT breakdown � Single-device level s-CNTs m-CNTs Collins, Science 2001 34

SDB Technique � Current-induced m-CNT breakdown � Single-device level Gate off s-CNTs m-CNTs Collins, Science 2001 35

SDB Technique � Current-induced m-CNT breakdown � Single-device level High Voltage Gate off Gnd s-CNTs m-CNTs Collins, Science 2001 36

SDB Technique � Current-induced m-CNT breakdown � Single-device level High Voltage Gate off Gnd m-CNT s-CNTs broken m-CNTs Collins, Science 2001 37

SDB Technique � Current-induced m-CNT breakdown � Single-device level Current density (µA / µm) 10 2 Before High Voltage After SDB SDB 10 1 Gate 10 0 off 10 -1 Gnd 10 0 10 2 10 4 10 6 m-CNT I on / I off s-CNTs broken m-CNTs Collins, Science 2001 38

Major SDB Challenges � Incorrect logic � m-CNT fragments � Impractical for giga-scale ICs � Internal node access 39

Incorrect Logic with SDB Vdd High Pull-up Network Output Contact High Wanted: off off B A (A + B) • (C + D) Intermediate Contact Got: Broken (C + D) off C D off Incorrect Logic ! Gnd Contact Gnd 40

VMR: m-CNT Immune Design � New approach: V LSI M etallic CNT R emoval � Sufficient • All logic designs � VLSI processing & design flows 41

VMR Example Final intended design VDD GND 42

VMR Steps 1. Grow and transfer CNTs s-CNTs m-CNTs (no gate control) ���������� !�"� ���������� !�"� ����������������� 43

VMR Steps VMR Electrodes VMR Electrodes VMR Electrodes VMR Electrodes VMR Electrodes 1. Grow and transfer CNTs 2. Fabricate VMR electrodes ���������� !�"� ����������������� Inter-digitated VMR electrodes Electrical breakdown friendly 44

VMR Steps VMR Electrodes VMR Electrodes VMR Electrodes VMR Electrodes VMR Electrodes 1. Grow and transfer CNTs 2. Fabricate VMR electrodes ���������� !�"� 3. Electrical breakdown (back-gate) ����������������� Inter-digitated VMR electrodes Electrical breakdown friendly High Gnd voltage 45