Carbon Nanotube Imperfection-Immune Digital VLSI Subhasish Mitra - - PowerPoint PPT Presentation

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Carbon Nanotube Imperfection-Immune Digital VLSI Subhasish Mitra - - PowerPoint PPT Presentation

Jul 10, 2023 120 likes •736 views

Carbon Nanotube Imperfection-Immune Digital VLSI Subhasish Mitra Robust Systems Group Department of EE & Department of CS Stanford University H. Chen, J. Deng, A. Hazeghi, A. Lin, N. Patil, M. Shulaker, L. Wei, H. Wei, Prof. H.-S. P. Wong,

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SLIDE 1

Carbon Nanotube Imperfection-Immune Digital VLSI

  • H. Chen, J. Deng, A. Hazeghi, A. Lin, N. Patil, M. Shulaker, L. Wei, H. Wei, Prof. H.-S. P. Wong, J. Zhang

Subhasish Mitra

Robust Systems Group Department of EE & Department of CS Stanford University

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SLIDE 2

Carbon Nanotube (CNT) Diameter (D) : 0.5 - 3 nm

D

  • S. Iijima

Carbon Nanotube FET (CNFET)

2

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SLIDE 3

Ideal CNFET Inverter

N+ doped Semiconducting CNTs Gates

Input

P+ doped Semiconducting CNTs

Lithographic pitch

4nm

Sub-lithographic pitch

Output

Vdd Gnd

3

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SLIDE 4

CNFET Technology Milestones

4

1998 First CNFET demonstration [Delft, IBM] 1998 First CNFET demonstration [Delft, IBM] 2001 Single-CNT logic gates [IBM] 2001 Single-CNT logic gates [IBM] 2006 Single-CNT ring osc. [IBM] 2006 Single-CNT ring osc. [IBM] 2004 Best single-CNT CNFET [Stanford] 2004 Best single-CNT CNFET [Stanford]

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SLIDE 5

CNFETs: BIG Promise, BUT

Major barriers for a decade

Mis-positioned nanotubes Metallic nanotubes

Processing alone inadequate

Imperfection-immune design essential

5

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SLIDE 6

Wanted: (A+C) (B+D) Got : B+D

Out A B C D Vdd A C B D Gnd

Wanted: A′C′ + B′D′ Got: A′C′ + B′D′ + A′D′

Mis-positioned CNTs

  • Incorrect Logic

6

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SLIDE 7

Semiconducting CNT (s-CNT) Metallic CNT (m-CNT) CNFET with s-CNT CNFET with m-CNT

Metallic CNTs

Typical: 10 – 50% grown CNTs metallic

Current Vg

Transistor

Vg Current

No gate control

7

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SLIDE 8

Results

Yesterday

SSI single-CNT ring oscillator

Today

Imperfection-immune VLSI circuits

8

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SLIDE 9

CNFET Technology Milestones

9

1998 First CNFET demonstration [Delft, IBM] 2001 Single-CNT logic gates [IBM] 2001 Single-CNT logic gates [IBM] 2006 Single-CNT ring osc. [IBM] 2006 Single-CNT ring osc. [IBM] 2004 Best single-CNT CNFET [Stanford] 2004 Best single-CNT CNFET [Stanford] 2008 Mis-positioned- CNT-immune VLSI logic gates [Stanford] 2008 Flexible CNT circuits [UIUC] 2009 Imperfection- immune adders & latches [Stanford] 2009 Defect- tolerant logic gates [USC] 2009 Monolithic 3D CNT circuits [Stanford] 2010 Ultra-short channel CNFETs [IBM]

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SLIDE 10

CNFET Technology Outlook

Problem Challenge Status CNT alignment & positioning Correct function Metallic CNT Correct function Low leakage CNT density High current density CNT doping Complementary CNFETs

10

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SLIDE 11

Outline

Introduction Mis-positioned-CNT-immune logic Metallic-CNT-immune logic CNT variations Conclusion

11

Patil, IEEE TCAD 2008, Symp. VLSI Tech. 2008

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SLIDE 12
  • 1. Grow CNTs

Mis-positioned-CNT-Immune NAND

12

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SLIDE 13

B A A B Out

  • 1. Grow CNTs
  • 2. Extended gate & contacts

CRUCIAL

13

Mis-positioned-CNT-Immune NAND

Vdd Gnd

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SLIDE 14

B A A B Out

  • 1. Grow CNTs
  • 2. Extended gate & contacts
  • 3. Etch gate & CNTs
  • 4. Chemically dope P & N regions

Vdd Gnd

14

Mis-positioned-CNT-Immune NAND

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SLIDE 15

B A A B Out

  • 1. Grow CNTs
  • 2. Extended gate & contacts
  • 3. Etch gate & CNTs
  • 4. Chemically dope P & N regions

Etched region ESSENTIAL

Graph algorithms

All possible functions

Vdd Gnd

15

Mis-positioned-CNT-Immune NAND

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SLIDE 16

Automated Algorithms

Given: Layout

Determine

  • Mis-positioned-CNT immune ?

16

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SLIDE 17

Mis-positioned-CNT-Immune NAND

17

E

Doped Doped

Gate B

Contact

Doped Contact Gate A Doped

Etched

1 1 A B 1 1

Contact Contact B Contact Contact A GA GB Intended: A or B

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SLIDE 18

Mis-positioned-CNT-Immune NAND

18

E

Doped Doped

Gate B

Contact

Doped Contact Gate A Doped

Etched

C-D-A-D-C : A

1 1 A B 1 1

Contact Contact B Contact Contact A GA GB Intended: A or B

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SLIDE 19

Mis-positioned-CNT-Immune NAND

19

Gate B

Contact

Doped Contact Gate A Doped

Etched

C-D-A-D-C : A C-D-B-D-C : B

1 1 A B 1 1

B Contact Contact A

E

Doped Doped Contact Contact GA GB Intended: A or B

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SLIDE 20

Mis-positioned-CNT-Immune NAND

20

E

Doped Doped

Gate B

Contact

Doped Contact Gate A Doped

Etched

C-D-A-D-C : A C-D-B-D-C : B C-D-B-D-A-D-B-D-C : A & B

1 1 A B 1 1

Contact Contact B Contact Contact A GA GB Intended: A or B

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SLIDE 21

Mis-positioned-CNT-Immune NAND

21

E

Doped Doped

Gate B

Contact

Doped Contact Gate A Doped

Etched

C-D-A-D-C : A C-D-B-D-C : B C-D-B-D-A-D-B-D-C : A & B C-D-E-D-C : 0 …

1 1 A B 1 1

Contact Contact B Contact Contact A GA GB Intended: A or B

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SLIDE 22

Mis-positioned-CNT-Immune NAND

22

E

Doped Doped

Gate B

Contact

Doped Contact Gate A Doped

Etched

Intended: A or B Implemented: A or B or (A & B) or 0 == A or B C-D-A-D-C : A C-D-B-D-C : B C-D-B-D-A-D-B-D-C : A & B C-D-E-D-C : 0 …

1 1 A B 1 1

Contact Contact B Contact Contact A GA GB

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SLIDE 23

Automated Algorithms

Given: Logic function

Produce

  • Mis-positioned-CNT immune layout

23

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SLIDE 24

Mis-positioned-CNT-Immune Layout

24

Gates

Out = A + (B + C)(D + E) Etched regions

CNTs

C B

Vdd / Gnd Contact

A

Output Contact

E D

Intermediate Contact

Immune to LARGE number of mis-positioned CNTs Efficient

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SLIDE 25

Most Importantly

VLSI processing

No die-specific customization

VLSI design flow

Immune library cells

25

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SLIDE 26

CNT Growth on Silicon Substrates

Highly mis-positioned

Not desirable for VLSI

26

10 µm 4 µm

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SLIDE 27

27

SEM image (grown CNTs) Quartz wafer with catalyst Aligned CNT growth 99.5% CNTs aligned Quartz wafer

First Wafer-Scale Aligned CNT Growth

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SLIDE 28

28

Silicon substrates for VLSI Low temperature (90oC – 120oC) processing

2 µm 2 µm Before transfer After transfer Target Substrate (SiO2/Si) Source Substrate (Quartz) Thermal Release Adhesive Tape

Wafer-Scale CNT Transfer

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SLIDE 29

29

First VLSI Demonstration

10µm 10µm 10µm

Mis-positioned-CNT-immune logic gates NAND, NOR, AND-OR-INV, OR-AND-INV

NOR pullup Etched Region

  • NAND pullup
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SLIDE 30

Outline

Introduction Mis-positioned-CNT-immune logic Metallic-CNT-immune logic CNT variations Conclusion

30

Patil, IEDM 2009, Shulaker, Nanoletters 2011, Wei, IEDM 2009, Symp. VLSI Tech. 2010

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SLIDE 31

Semiconducting CNT (s-CNT) Metallic CNT (m-CNT) CNFET with s-CNT CNFET with m-CNT

Metallic CNTs

Typical: 10 – 50% grown CNTs metallic

Current Vg

Transistor

Vg Current

No gate control

31

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SLIDE 32

m-CNT Processing Options

Grow 0% m-CNTs

Open challenge

Remove m-CNTs after growth

99.99% removal required

32

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SLIDE 33

Existing m-CNT Removal

Sort CNTs

Inadequate

SDB

Single Device electrical Breakdown Not scalable

33

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SLIDE 34

SDB Technique

Current-induced m-CNT breakdown

Single-device level

34

m-CNTs s-CNTs

Collins, Science 2001

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SLIDE 35

SDB Technique

Current-induced m-CNT breakdown

Single-device level

35

m-CNTs s-CNTs

Collins, Science 2001

Gate

  • ff
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SLIDE 36

SDB Technique

Current-induced m-CNT breakdown

Single-device level

36

m-CNTs s-CNTs

Collins, Science 2001

Gate

  • ff

High Voltage Gnd

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SLIDE 37

SDB Technique

Current-induced m-CNT breakdown

Single-device level

37

m-CNTs s-CNTs

Collins, Science 2001

Gate

  • ff

High Voltage Gnd

m-CNT broken

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SLIDE 38

SDB Technique

Current-induced m-CNT breakdown

Single-device level

38

m-CNTs s-CNTs

Collins, Science 2001

Gate

  • ff

High Voltage Gnd

m-CNT broken

Current density (µA / µm) 102 101 100 10-1 100 102 104 106 Ion / Ioff

Before SDB After SDB

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SLIDE 39

Major SDB Challenges

Incorrect logic

m-CNT fragments

Impractical for giga-scale ICs

Internal node access

39

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SLIDE 40

Incorrect Logic with SDB

40

Output Contact Gnd Contact Intermediate Contact A B C D

  • ff
  • ff
  • ff
  • ff

Gnd High Broken High Pull-up Network Vdd

Incorrect Logic !

Wanted: (A + B) • (C + D) Got: (C + D)

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SLIDE 41

VMR: m-CNT Immune Design

New approach: VLSI Metallic CNT Removal

Sufficient

  • All logic designs

VLSI processing & design flows

41

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SLIDE 42

Final intended design

VDD GND

VMR Example

42

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SLIDE 43

m-CNTs (no gate control) s-CNTs

  • !"
  • 1. Grow and transfer CNTs

VMR Steps

!"

43

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SLIDE 44
  • 2. Fabricate VMR electrodes
  • 1. Grow and transfer CNTs
  • !"

VMR Electrodes VMR Electrodes VMR Electrodes VMR Electrodes VMR Electrodes

Inter-digitated VMR electrodes Electrical breakdown friendly

44

VMR Steps

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SLIDE 45
  • 2. Fabricate VMR electrodes
  • 3. Electrical breakdown (back-gate)
  • 1. Grow and transfer CNTs

High voltage Gnd

  • !"

VMR Electrodes VMR Electrodes VMR Electrodes VMR Electrodes VMR Electrodes

Inter-digitated VMR electrodes Electrical breakdown friendly

45

VMR Steps

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SLIDE 46
  • 2. Fabricate VMR electrodes
  • 3. Electrical breakdown (back-gate)
  • 4. Etch CNTs : predefined regions

(mis-positioned-CNT-immune design)

  • 5. Etch unneeded VMR electrodes
  • 1. Grow and transfer CNTs

CNFET contacts not removed

46

VMR Steps

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SLIDE 47
  • 2. Fabricate VMR electrodes
  • 3. Electrical breakdown (back-gate)
  • 4. Etch CNTs : predefined regions

(mis-positioned-CNT-immune design)

  • 5. Etch unneeded VMR electrodes
  • 6. Top-gates (mis-positioned-CNT-immune design), doping, wires
  • 1. Grow and transfer CNTs

47

VMR Steps

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SLIDE 48

Theorem

48

VMR works for arbitrary logic design

if

Any two transistors in series

Connected through contact

  • Minimum pitch

Immune library cells: very small impact

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SLIDE 49

First Experimental Demonstration

49

Half-adder Sum D-latch

Imperfection-immune CNT VLSI circuits Arithmetic & storage elements

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SLIDE 50

First Monolithic CNT 3D ICs

50

Conventional via, NOT TSV 2-layer CNT XOR

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SLIDE 51

Outline

Introduction Mis-positioned-CNT-immune logic Metallic-CNT-immune logic CNT variations Conclusion

51

Zhang, IEEE TCAD 2009, DAC 2009, DAC 2010

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SLIDE 52

CNT Variations Challenging

Probabilistic modeling essential [Borkar 07]

52

CNFET Ion variations

Others CNT diameter variations

CNT density variations m-CNTs

Channel length variations

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SLIDE 53

Probabilistic CNT Growth Model

Probability (m-CNT) = pm Probability (s-CNT) = ps = 1 - pm

53 2

2 1 3 0.22 3 3

  • =
  • s-CNT

m-CNT

3

1 0.04 3

  • =
  • 3

2 0.3 3

  • =
  • 2

1 2 3 0.44 3 3

  • =
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SLIDE 54

m-CNT Removal Alone Inadequate

54

m-CNTs removed s-CNTs intact

m-CNT

Must be highly unlikely

No CNTs left !

  • prob. = (pm)3

= (33%)3 = 4%

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SLIDE 55

Probabilistic Design a MUST

55

Design Processing

% grown m-CNTs CNT density variations Special layouts CNFET sizing

Processing & Design Co-Optimization Leakage Noise margin Delay variations

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SLIDE 56

Special Layouts

56

Yield

low high low high CNT variation- agnostic design Upsize CNFETs

New technique

Aligned-active layouts Engineered CNT correlations

1 Cost

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SLIDE 57

Outline

Introduction Mis-positioned-CNT-immune logic Metallic-CNT-immune logic CNT variations Conclusion

57

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SLIDE 58

Thanks to our Sponsors

Photo credits:

  • H. Dai, ibm.com, Nanoletters, Nature, Science, Stanford, Wikipedia

58

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SLIDE 59

CNFET Technology Outlook

Problem Challenge Status CNT alignment & positioning Correct function Metallic CNT Correct function Low leakage CNT density High current density CNT doping Complementary CNFETs

59

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SLIDE 60

Conclusion

Imperfection-immune design essential

New solutions: practical, elegantly simple

60

Next challenge: CNT variations

CNT correlation unique layouts