a LOW POWER, LOW VOLTAGE ADC DESIGN ISSUES I Typical Supply - - PowerPoint PPT Presentation

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8.0 PRACTICAL DESIGN TECHNIQUES FOR SENSOR SIGNAL CONDITIONING 1 Introduction 2 Bridge Circuits 3 Amplifiers for Signal Conditioning 4 Strain, Force, Pressure, and Flow Measurements 5 High Impedance Sensors 6 Position and Motion Sensors 7 Temperature Sensors I 8 ADCs for Signal Conditioning 9 Smart Sensors 10 Hardware Design Techniques

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8.1 LOW POWER, LOW VOLTAGE ADC DESIGN ISSUES

I Typical Supply Voltages: ±5V, +5V, +5/+3V, +3V I Lower Signal Swings Increase Sensitivity to All Types of Noise (Device, Power Supply, Logic, etc.) I Device Noise Increases at Low Currents I Common Mode Input Voltage Restrictions I Input Buffer Amplifier Selection Critical I Auto-Calibration Modes Desirable at High Resolutions

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8.2 ADCs FOR SIGNAL CONDITIONING

I Successive Approximation N Resolutions to 16-bits N Minimal Throughput Delay Time N Used in Multiplexed Data Acquisition Systems I Sigma-Delta N Resolutions to 24-bits N Excellent Differential Linearity N Internal Digital Filter, Excellent AC Line Rejection N Long Throughput Delay Time N Difficult to Multiplex Inputs Due to Digital Filter Settling Time I High Speed Architectures: N Flash Converter N Subranging or Pipelined

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8.3 SUCCESSIVE APPROXIMATION ADC

SHA SUCCESSIVE APPROXIMATION REGISTER (SAR) DAC TIMING CONVERT START EOC, DRDY, OR BUSY OUTPUT ANALOG INPUT COMPARATOR

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8.4 3-BIT SWITCHED CAPACITOR DAC

_ + C/ 4 C/ 2 C C/ 4 AIN VREF SIN SC

S1 S2 S3 S4

BIT1 (MSB) BIT2 BIT3 (LSB) SWITCHES SHOWN IN TRACK (SAMPLE) MODE

A

CTOTAL = 2C

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8.5 RESOLUTION / CONVERSION TIME COMPARASION FOR REPRESENTATIVE SINGLE-SUPPLY SAR ADCs

AD7472 AD7891 AD7858/59 AD7887/88 AD7856/57 AD974 AD7670 RESOLUTION 12-BITS 12-BITS 12-BITS 12-BITS 14-BITS 16-BITS 16-BITS SAMPLING RATE 1.5MSPS 500kSPS 200kSPS 125kSPS 285kSPS 200kSPS 1MSPS POWER 9mW 85mW 20mW 3.5mW 60mW 120mW 250mW CHANNELS 1 8 8 8 8 4 1

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8.6 TYPICAL SAR ADC TIMING

CONVST CONVERSION TIME SAMPLE X SAMPLE X+1 SAMPLE X+2 DATA X DATA X+1 OUTPUT DATA EOC, BUSY TRACK/ ACQUIRE CONVERSION TIME TRACK/ ACQUIRE

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8.7 12-BIT TWO-STAGE PIPELINED ADC ARCHITECTURE

SHA 1 SHA 2 TIMING 6-BIT ADC 6-BIT DAC BUFFER REGISTER + _ 7-BIT ADC ERROR CORRECTION LOGIC OUTPUT REGISTERS 6 6 7 12 12 ANALOG INPUT SAMPLING CLOCK OUTPUT DATA

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8.8 TYPICAL PIPELINED ADC TIMING

SAMPLING CLOCK SAMPLE X SAMPLE X+1 SAMPLE X+2 DATA X–2 DATA X–1 DATA X OUTPUT DATA ABOVE SHOWS TWO CLOCK-CYCLES PIPELINE DELAY

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8.9 DRIVING SWITCHED CAPACITOR INPUTS OF AD7858/59 12-BIT, 200kSPS ADC

AD820 _ + + _ CAP DAC

10kΩ Ω 10kΩ Ω 10.7kΩ Ω 10kΩ Ω 50Ω Ω 10nF 125Ω Ω 125Ω Ω 20pF T H H T VREF AIN+ AIN– DGND AGND AVDD DVDD 0.1µF 0.1µF +2.5V +1.30V +3V TO +5V VIN VIN : 0V TO +2.5V AIN+ : +2.6V TO +0.1V

AD7858/59

CUTOFF = 320kHz 0.1µF VCM = NOTE: ONLY ONE INPUT SHOWN T = TRACK H = HOLD 10kΩ Ω 412Ω Ω +100mV 0.1µF 0.1µF

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8.10 DRIVING SINGLE-SUPPLY ADCs WITH SCALED INPUTS

+2.5V REFERENCE + _

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REFOUT/ REFIN VINX AGND RS 2kΩ Ω R2 7.5kΩ Ω R3 10kΩ Ω 30kΩ Ω +2.5V TO ADC REF CIRCUITS TO MUX, SHA, ETC. ±10V 0V TO +2.5V

AD7890-10 12-BITS, 8-CHANNEL

VS R1 R1, R2, R3 ARE RATIO-TRIMMED THIN FILM RESISTORS +5V

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8.11 BASIC CMOS ANALOG SWITCH

P-CH N-CH P-CH N-CH VIN VOUT +VS –VS –VS +VS OFF ON + – SIGNAL VOLTAGE RON NMOS PMOS CMOS

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8.12 SIMPLIFIED DIAGRAM OF A TYPICAL ANALOG MULTIPLEXER

ADDRESS REGISTER ADDRESS DECODER

RON RON

CHANNEL ADDRESS CHANNEL 1 CHANNEL M CLOCK BUFFER, SHA, OR PGA RL

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8.13 WHAT'S NEW IN DISCRETE SWITCHES / MUXES?

I ADG508F, ADG509F, ADG527F: ±15V Specified N RON < 300Ω Ω N Switching Time < 250ns N Fault Protection on Inputs and Outputs (–40V to + 55V) I ADG451, ADG452, ADG453: ±15V, +12V, ±5V Specified N RON < 5Ω Ω N Switching Time < 180ns N 2kV ESD Protection I ADG7XX-Family: Single-Supply, +1.8V to +5.5V N RON < 5Ω Ω, RON Flatness < 2Ω Ω N Switching Time < 20ns

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8.14 MULTIPLEXED SAR ADC FILTERING AND TIMING

MUX LPF1 LPFM SHA ADC LPFC CHANGE CHANNEL CONVST, fs CONVST CONVERT EOC, BUSY TRACK/ ACQUIRE MUX OUTPUT MUX SETTLING MUX SETTLING CHANGE CHANNEL CHANGE CHANNEL CONVERT TRACK/ ACQUIRE CHANGE CHANNEL DATA EOC, BUSY AIN1 AINM fs / 2M fs fc SEE TEXT

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8.15 SINGLE-POLE FILTER SETTLING TIME TO REQUIRED ACCURACY

RESOLUTION # OF BITS 6 8 10 12 14 16 18 20 22 LSB (%FS) 1.563 0.391 0.0977 0.0244 0.0061 0.00153 0.00038 0.000095 0.000024 # OF TIME CONSTANTS, n 4.16 5.55 6.93 8.32 9.70 11.09 12.48 13.86 15.25 fc/fs 0.67 0.89 1.11 1.32 1.55 1.77 2.00 2.22 2.44 fs = ADC Sampling Frequency fc = Cutoff Frequency of LPFC

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8.16 AD7858 12-BIT, 200kSPS 8-CHANNEL SINGLE-SUPPLY ADC

MUX T/H 2.5V REF BUF SWITCHED CAPACITOR DAC CALIBRATION MEMORY AND CONTROLLER SAR + ADC CONTROL SERIAL INTERFACE/CONTROL REGISTER AIN1 REFIN/ REFOUT CREF1 CREF2 CAL DVDD AVDD AGND DGND CLKIN CONVST BUSY SLEEP SYNC DIN DOUT SCLK AIN8

AD7858/ AD7858L

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8.17 AD7858 / AD7858L DATA ACQUISITION ADCs KEY SPECIFICATIONS

I 12-Bit, 8Channel, 200kSPS (AD7858), 100kSPS (AD7858L) I System and Self-Calibration with Autocalibration on Power-Up I Automatic Power Down After Conversion (25µW) I Low Power: N AD7858: 15mW (VDD = +3V) N AD7858L: 5.5mW (VDD = +3V) I Flexible Serial Interface: 8051 / SPI / QSPI / µP Compatible I 24-Pin DIP, SOIC, SSOP Packages I AD7859, AD7859L: Parallel Output Devices, Similar Specifications

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8.18 SIGMA-DELTA ADCs

I Low Cost, High Resolution (to 24-bits) Excellent DNL, I Low Power, but Limited Bandwidth I Key Concepts are Simple, but Math is Complex N Oversampling N Quantization Noise Shaping N Digital Filtering N Decimation I Ideal for Sensor Signal Conditioning N High Resolution N Self, System, and Auto Calibration Modes

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8.19 OVERSAMPLING, DIGITAL FILTERING, NOISE SHAPING, AND DECIMATION

fs 2 fs Kfs 2 Kfs Kfs Kfs 2 fs 2 fs 2 DIGITAL FILTER REMOVED NOISE REMOVED NOISE QUANTIZATION NOISE = q / 12 q = 1 LSB ADC ADC DIGITAL FILTER Σ∆ Σ∆ MOD DIGITAL FILTER fs Kfs Kfs DEC fs Nyquist Operation Oversampling + Digital Filter + Decimation Oversampling + Noise Shaping + Digital Filter + Decimation

A B C

DEC fs

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8.20 FIRST-ORDER SIGMA-DELTA ADC ∑

∫

+ _ +VREF –VREF

DIGITAL FILTER AND DECIMATOR

+ _ CLOCK Kfs VIN N-BITS fs fs A B 1-BIT DATA STREAM 1-BIT DAC

LATCHED COMPARATOR (1-BIT ADC) 1-BIT, Kfs

SIGMA-DELTA MODULATOR

INTEGRATOR

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8.21 SIMPLIFIED FREQUENCY DOMAIN LINEARIZED MODEL OF A SIGMA-DELTA MODULATOR ∑

ANALOG FILTER H(f) = 1 f

∑

X Y + _ X – Y 1 f ( X – Y ) Q = QUANTIZATION NOISE Y = 1 f ( X – Y ) + Q REARRANGING, SOLVING FOR Y: Y = X f + 1 + Q f f + 1 SIGNAL TERM NOISE TERM Y

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8.22 SIGMA-DELTA MODULATORS SHAPE QUANTIZATION NOISE

fs 2 Kfs 2 2ND ORDER 1ST ORDER DIGITAL FILTER

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8.23 SECOND-ORDER SIGMA-DELTA ADC ∑

∫

+ _ VIN

INTEGRATOR

∑

∫

+ _ CLOCK Kfs 1-BIT DAC

INTEGRATOR

DIGITAL FILTER AND DECIMATOR N-BITS fs + _ 1-BIT DATA STREAM

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8.24 SNR VERSUS OVERSAMPLING RATIO FOR FIRST, SECOND, AND THIRD-ORDER LOOPS

FIRST-ORDER LOOP 9dB / OCTAVE SECOND-ORDER LOOP 15dB / OCTAVE THIRD-ORDER LOOP* 21dB / OCTAVE

* > 2nd ORDER LOOPS DO NOT OBEY LINEAR MODEL 4 8 16 32 64 128 256 20 40 60 80 100 120 SNR (dB) OVERSAMPLING RATIO, K

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8.25 EFFECT OF INPUT-REFERRED NOISE ON ADC "GROUNDED INPUT" HISTOGRAM

n n+1 n+2 n+3 n+4 n–1 n–2 n–3 n–4

NUMBER OF OCCURANCES RMS NOISE P-P INPUT NOISE

≈ 6.6 × RMS NOISE

OUTPUT CODE

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8.26 DEFINITION OF "NOISE-FREE" CODE RESOLUTION

EFFECTIVE RESOLUTION = log2 FULLSCALE RANGE RMS NOISE BITS NOISE-FREE CODE RESOLUTION = log2 FULLSCALE RANGE P-P NOISE BITS P-P NOISE = 6.6 × RMS NOISE NOISE-FREE CODE RESOLUTION = log2 FULLSCALE RANGE 6.6 × RMS NOISE BITS = EFFECTIVE RESOLUTION – 2.72 BITS

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8.27 AD7730 SINGLE-SUPPLY BRIDGE ADC

MUX

∑ ∑

PGA SIGMA- DELTA MODULATOR PROGRAMMABLE DIGITAL FILTER REFERENCE DETECT CALIBRATION MICROCONTROLLER 6-BIT DAC + +/– AC EXCITATION CLOCK CLOCK GENERATION REGISTER BANK SIGMA-DELTA ADC SERIAL INTERFACE AND CONTROL LOGIC VBIAS AIN1(+) AIN1(–) AIN2(+)/D1 AIN2(–)/D0 ACX ACX AVDD DVDD REFIN(–) REFIN(+) STANDBY SYNC MCLK IN MCLK OUT SCLK CS DIN DOUT AGND DGND POL RDY RESET 100nA 100nA BUFFER

AD7730

+ _

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8.28 AD7730 KEY SPECIFICATIONS

I Resolution of 80,000 Counts Peak-to-Peak (16.5-Bits) for ± 10mV Fullscale Range I Chop Mode for Low Offset and Drift I Offset Drift: 5nV/°C (Chop Mode Enabled) I Gain Drift: 2ppm/°C I Line Frequency Common Mode Rejection: > 150dB I Two-Channel Programmable Gain Front End I On-Chip DAC for Offset/TARE Removal I FASTStep Mode I AC Excitation Output Drive I Internal and System Calibration Options I Single +5V Supply I Power Dissipation: 65mW, (125mW for 10mV FS Range) I 24-Lead SOIC and 24-Lead TSSOP Packages

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8.29 AD7730 DIGITAL FILTER FREQUENCY RESPONSE

–10 –20 –30 –40 –50 –60 –70 –80 –90 –110 –120 –130 0 10 20 30 40 50 60 70 80 90 100 GAIN (dB) FREQUNCY (Hz) SINC3 + 22-TAP FIR FILTER, CHOP MODE ENABLED

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8.30 AD7730 DIGITAL FILTER SETTLING TIME SHOWING FASTStep™ MODE

0 5 10 15 20 25 20,000,000 15,000,000 10,000,000 5,000,000 CODE NUMBER OF OUTPUT SAMPLES FASTStep ENABLED FASTStep DISABLED

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8.31 AD7730 SIGMA-DELTA ADC CALIBRATION OPTIONS

I Internal Zero-ScaleCalibration N 22 Output Cycles (CHP = 0) N 24 Output Cycles (CHP = 1) I Internal Full-Scale Calibration N 44 Output Cycles (CHP = 0) N 48 Output Cycles (CHP = 1) I Calibration Programmed via the Mode Register I Calibration Coefficients Stored in Calibration Registers I External Microprocessor Can Read or Write to Calibration Coefficient Registers

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8.32 AD7730 BRIDGE APPLICATION (SIMPLIFIED SCHEMATIC)

+5V AVDD AGND + AIN – AIN + VREF – VREF RLEAD RLEAD 6-LEAD BRIDGE

AD7730 ADC 24 BITS

+SENSE – SENSE

VO

+FORCE – FORCE DVDD +5V/+3V DGND

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8.33 DRIVING UNBUFFERED AD77XX-SERIES Σ∆ Σ∆ ADC INPUTS

HIGH IMPEDANCE > 1GΩ Ω SWITCHING FREQ DEPENDS ON fCLKIN AND GAIN CINT 10pF TYP REXT RINT 7kΩ Ω

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REXT Increases CINT Charge Time and May Result in Gain Error Charge Time Dependent on the Input Sampling Rate and Internal PGA Gain Setting Refer to Specific Data Sheet for Allowable Values of REXT to Maintain Desired Accuracy Some AD77XX-Series ADCs Have Internal Buffering Which Isolates Input from Switching Circuits AD77XX-Series

(WITHOUT BUFFER) VSOURCE

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8.34 SYNCHRONIZING MULTIPLE SIGMA-DELTA ADCs IN SIMULTANEOUS SAMPLING APPLICATIONS

SIGMA-DELTA ADC

÷ K

SIGMA-DELTA ADC Kfs fs DATA OUTPUT DATA OUTPUT ANALOG INPUTS SYNC SYNC

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8.35 AD7716 MULTICHANNEL SIGMA-DELTA ADC

ANALOG MODULATOR LOW PASS DIGITAL FILTER ANALOG MODULATOR LOW PASS

DIGITAL

FILTER ANALOG MODULATOR LOW PASS DIGITAL FILTER ANALOG MODULATOR LOW PASS DIGITAL FILTER CONTROL LOGIC OUTPUT SHIFT REGISTER CONTROL REGISTER CLOCK GENERATION

AVDD DVDD AVSS RESET A0 A1 A2 CLKIN CLKOUT VREF AGND DGND DIN1 DOUT1 DOUT2 MODE CASCIN CASCOUT RFS SDATA SCLK DRDY TFS AIN1 AIN2 AIN3 AIN4

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8.36 AD7716 KEY SPECIFICATIONS

I Up to 22-Bit Resolution, 4 Input Channels I Sigma-Delta Architecture, 570kSPS Oversampling Rate I On-Chip Lowpass Filter, Programmable from 36.5Hz to 584Hz I Serial Input / Output Interface I ±5V Power Supply Operation I 50mW Power Dissipation

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8.37 BASICS OF POWER MEASUREMENTS

v(t) = V × cos(ω

ωt)

(Instantaneous Voltage) i(t) = I × cos(ω

ωt)

(Instantaneous Current) p(t) = V × I cos2(ω

ωt)

(Instantaneous Power) V × I 2 = 1 + cos(2ω

ωt)

p(t) Average Value of p(t) = Instantaneous Real Power Includes Effects of Power Factor and Waveform Distortion

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8.38 AD7750 PRODUCT-TO-FREQUENCY CONVERTER

×16 2ND ORDER SIGMA-DELTA MODULATOR ×2 2ND ORDER SIGMA-DELTA MODULATOR DIGITAL HIGHPASS FILTER DELAY DIGITAL LOWPASS FILTER DIGITAL TO FREQUENCY CONVERTER DIGITAL TO FREQUENCY CONVERTER 2.5V BANDGAP REFERENCE G1 VDD ACDC REVP CLK OUT CLK IN F1 F2 FOUT AGND REFOUT REFIN FS S1 S2 DGND V1+ V1– V2+ V2– + _ + _

AD7750

Instantaneous Real Power Instantaneous Power

(CURRENT) (VOLTAGE)

= v(t) × i(t) v(t) i(t)

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8.39 AD7750 SINGLE PHASE POWER METER APPLICATION (SIMPLIFIED SCHEMATIC)

×16 ADC 1 + HPF ×2 ADC2 + _ + _ LOWPASS FILTER + DIGITAL TO FREQUNCY CONVERTER

0 0 0 5 1 4 7

AC TO DC SUPPLY kW-Hr COUNTER +5V PHASE (HOT) NEUTRAL TO LOAD CALIBRATION LED REVERSE POLARITY LED

AD7750

i(t) v(t) REVP F1 F2 FOUT