A Calibration concept for SAR ADC for operation in LAr TPC Name: Yuan Mei Brookhaven National Laboratory Instrumentation Division ULITIMA 2018 yuanmei@bnl.gov Yuan Mei 9/11/2018 1
Motivation ▪ Design a 12-bit ADC running 2MS/s for DUNE ▪ Risk mitigation for cold temperature @77K ▪ Errors from analog circuits should be overcome with digital calibration , transferring complexity from analog to digital domain 9/11/2018 Yuan Mei 2
SAR ADC Architecture Comparator Vin Digital Outputs SAR Logic DAC • Bottom plate sampling method with synchronous timing • 12-bit resolution with 14 conversion-cycle ( 2-bit redundancy ) • Digital foreground calibration implemented 9/11/2018 Yuan Mei 3
Static Error sources • Conversion accuracy is subject to the non-idealities of analog components, the main error source are DAC mismatch and comparator offset errors. • SAR only has one comparator, offset won’t affect linearity. • Bottom-plate sampling is performed, thus injected charge to the top- plate is independent of input signal and contribute a fixed offset • Auto-zeroing and chopper techniques are often used to eliminate comparator offset • Capacitor mismatch is fatal to ADC performance if not solved 9/11/2018 Yuan Mei 4
Capacitor mismatch issues • 12-bit matching is needed in the capacitor array o Random mismatch: Gaussian distribution o Gradient mismatch: Location-dependent o Routing mismatch: Layout dependent • Unit-cap and common-centroid layout can fix gradient mismatch and routing mismatch • Random mismatch can be solved by using larger unit-capacitor [1] or using calibration method 9/11/2018 Yuan Mei 5
Capacitor mismatch in DAC DAC mismatch limit ADC performance and calibration would improve ADC! 9/11/2018 Yuan Mei 6
Id Idea of f Digital Calibration • Post-processing of codes o Relies on digital signal processing o No feedback to ADC and thus no stability issue o Doesn’t required complex analog circuit o Digital circuits scale in advanced process Correlation-based calibration is selected for this prototype 9/11/2018 Yuan Mei 7
Correlation-based Calibration • Inject a small amount of analog signal that is uncorrelated with the input signal. Since it passes through the same path as DAC signal, it encounter same non-idealities and hence can detect the mismatch error • Using a statistical correlator (histogram method) or the least mean square ( LMS ) algorithm, the inject signal can be “correlated out” in the digital back-end and capacitor mismatch error are estimated in the process [2] 9/11/2018 Yuan Mei 8
Im Implementation of f Algorithm W2 D2 Encode 2 d2 Vin SAR dout CORE a • a e[n] Each sampled analog signal will be digitized twice d1 D1 Encode 1 LMS Calibration 2 • d Decimal output codes d1 and d2 will create a error function W1 engine • Error function will provide information to infer the unknown weighting vector W LMS : W k [N+1] = W k [n] - µ*e[n]*d k [n] e [N] = d 1 [n] - d 2 [n] -2 d • Adaptive learning algorithm (LMS) to update weight coefficient in DAC in which error is gradually forced to zero Fig. Block diagram of the perturbation based digital calibration for SAR ADC [3] • Learning procedure converges, the mean of d1 and d2 will yield the correct digital output codes 9/11/2018 Yuan Mei 9
Capacitor ratio with redundancy 9/11/2018 Yuan Mei 10
Notes : Single-ended for simplicity Calibration circuit Implemented in differential Calibration Circuit VCM 10 1920 1024 544 288 144 80 40 24 8 2 1 12 6 2 MSB LSB Calibration Cap Vinput VCM Bootstrap_Switch Vref_pos Transmission-Gate Switch Vref_neg Transmission-Gate Switch Advantage Disadvantage Controlled by SAR • • Calibration circuit can be utilized in DAC Decrease input dynamic range Logic • Calibration circuit is stable at cold • Calibration control is simple 9/11/2018 Yuan Mei 11
Timing Diagram 40 Cycles Clk Reset Sample Input regeneration Output1 D1 D2 D14 D13 D12 Output2 D1b D2b D14b Timing diagram of the proposed calibration method • One complete conversion consist of a 5 clock-cycle sampling phase and two 14 clock-cycle conversion phases; • Besides, 1 clock-cycle is reserve for reset and 6 clock-cycle is for input regeneration. 9/11/2018 Yuan Mei 12
Simulations with digital calibration • Simulations are done in Cadence @ 77K temperature • All blocks are implemented and simulated in transistor level • Unit capacitor is MIM cap provided by foundry (about 10 fF) • DAC mismatch errors are the major error source 9/11/2018 Yuan Mei 13
Capacitor mismatch calibration verification • Set random mismatch on capacitor weights • Simulate to see if calibration can find the optimal weight and improve the performance • Other mismatch is excluded from this verfication 9/11/2018 Yuan Mei 14
Capacitor mismatch calibration Simulated with 2^14 (16,384) samples, weights are converged around 10,000 samples Y-axis: Capacitor weight X-axis: # of samples 9/11/2018 Yuan Mei 15
Capacitor mismatch calibration Simulated with 2^14 (16,384) samples, weights are converged around 10,000 samples Y-axis: Capacitor weight X-axis: # of samples 9/11/2018 Yuan Mei 16
Capacitor mismatch calibration With calibration, all the weights in the DAC are updated Y-axis: Capacitor weight X-axis: # of samples 9/11/2018 Yuan Mei 17
Dynamic test FFT points: 2^14 Without Calibration ENOB = 8.3 bits With Calibration ENOB= 11.2 bits • ENOB is improved • Dynamic range also improved 9/11/2018 Yuan Mei 18
Dynamic test FFT points: 2^17 Without Calibration ENOB = 8.3 bits With Calibration ENOB= 11.9 bits With more samples : • ENOB is further improved from 11.2bits to 11.9bits • Dynamic range also improved from 69.1 dB to 73.6dB 9/11/2018 Yuan Mei 19
Static test Sample points: 2^14 A lot missing codes! NO missing code! Without Calibration Without Calibration • Linearity is improved with the digital calibration 9/11/2018 Yuan Mei 20
Static test With samples 16,384 (2^14) With samples 131,072 (2^17) • Linearity is further improved with more samples 9/11/2018 Yuan Mei 21
Floorplan Digital Domain Analog Domain N-DAC DC Switches Vin- Bootstrap Switch Dummy Dummy Dummy Pre Dummy Dummy amp VCM N-DAC Switch Nomal Calibration Clock Generator Mode Mode Data Formatter Dummy Dummy Dummy Comparator SAR SAR +LVDS I/O Dummy Dummy Logic Logic VCM Dummy Dummy P-DAC Switch Pre amp Dummy Dummy Dummy Vin+ Bootstrap Switch P-DAC DC Switches Floorplan of SAR ADC prototype 9/11/2018 Yuan Mei 22
Die Photo Die photo of SAR ADC prototype 9/11/2018 Yuan Mei 23
Measurement • Chip came back in Mid-July and measurement will be done in October 9/11/2018 Yuan Mei 24
Power consumption @77K(Simulation by PEX) Block Name Power consumption 2MS/s Digital 240 µw Analog 280 µW Total 520 µW 9/11/2018 Yuan Mei 25
Acknowledgement • My colleagues : Gabriella Carini, Huchen Chen, Mietek Dabrowski, Shaorui Li , and Emerson Vernon • Fermi lab collaborators and their cold model for TSMC 65nm at 77K • DUNE and DoE for support of this work 9/11/2018 Yuan Mei 26
Reference [1] Yi-long Yu, ADI talk, A 12 bit 100MS/s two step hybrid ADC in 40nm CMOS with statistical calibration [2] Ahmed M. A. Ali. 2016. High Speed Data Converters . Institution of Engineering and Technology. [3] W. Liu, P. Huang and Y. Chiu , "A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration," in IEEE J. of Solid-State Circuits, vol. 46, no. 11, pp. 2661-2672, Nov. 2011 . 9/11/2018 Yuan Mei 27
Q & A Thank you for your attention. 9/11/2018 Yuan Mei 28
Backup slides LMS : W k [N+1] = W k [n] - µ*e[n]*d k [n] e [N] = d 1 [n] - d 2 [n] -2 d W i represents the respective bit weight. µ i is the step size of the update equation and is scaled according to the bit. e[N] is the total error of the Nth step. d N are the raw ADC output; Δ d are digitized offset of the inserting analog offset Δ a 9/11/2018 Yuan Mei 29
Convergence of f Error 9/11/2018 30
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