ADC Non-linearity Wenqiang Gu Brookhaven National Laboratory 1 - - PowerPoint PPT Presentation

Calibration of the ProtoDUNE ADC Non-linearity

Wenqiang Gu Brookhaven National Laboratory

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Outline

• ProtoDUNE TPC readout electronics
• ADC nonlinearity (NL) and other issues
• Motivation and idea of the NL calibration
• Validation with a Monte Carlo study
• Summary and working plan

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WIRE SIGNAL

• Cold preamplifier
• Gain: 4.7, 7.8, 14, or 25 mV/fC
• Shaping time: 0.5, 1.0, 2.0, or 3.0 µs
• Cold ADC (Analog to Digital Converter)
• Continuous time & amplitude  discrete t & amp.
• 12 bits: 4096 minimum steps in full range (1.2V)
• 2 MHz sampling rate

ProtoDUNE TPC readout electronics

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µBooNE: 14 mv/fC + 2.0 µs

• V. Radeka et al. Cold electronics for ‘Giant’ Liquid

Argon Time Projection Chambers,

• J. Phys. Conf. Ser. 308 (2011) 012021.

Readout scheme of ADC circuit

• 16 channels per ADC circuit

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FPGA Internal Pattern Generator 2:1 MUX RST READ IDXM IDXL IDL Clock 200MHz (100MHz) RST READ IDXM IDXL IDL FE ASIC CHN0 CHN15 Input Buffer ADC15 ADC0 D0 – D11 D0 – D11 FIFO CLK1:CLK0 2 Global bits (CLK1:CLK0)  00 or 11 : Control signals from internal logic  01: ADC control signals directly from FPGA

P1 ADC ASIC

• 12 bits /channel saved in FIFO buffer

e.g. 2048 = 100,000,000,000 Most significant bits (MSB) Least significant bits (LSB)

Readout scheme of ADC circuit

• 16 channels split into two readout chains from FIFO

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FPGA Internal Pattern Generator 2:1 MUX RST READ IDXM IDXL IDL Clock 200MHz (100MHz) RST READ IDXM IDXL IDL FE ASIC CHN0 CHN15 Input Buffer ADC15 ADC0 D0 – D11 D0 – D11 FIFO CLK1:CLK0 2 Global bits (CLK1:CLK0)  00 or 11 : Control signals from internal logic  01: ADC control signals directly from FPGA

P1 ADC ASIC

Readout scheme of ADC circuit

• The read/write logic must be synchronized through five control

signals

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FPGA Internal Pattern Generator 2:1 MUX RST READ IDXM IDXL IDL Clock 200MHz (100MHz) RST READ IDXM IDXL IDL FE ASIC CHN0 CHN15 Input Buffer ADC15 ADC0 D0 – D11 D0 – D11 FIFO CLK1:CLK0 2 Global bits (CLK1:CLK0)  00 or 11 : Control signals from internal logic  01: ADC control signals directly from FPGA

P1 ADC ASIC

Readout scheme of ADC circuit

• These five signals can be generated internally inside the ADC by a 200

MHz clock (2 MHz digitization) or taken externally

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FPGA Internal Pattern Generator 2:1 MUX RST READ IDXM IDXL IDL Clock 200MHz (100MHz) RST READ IDXM IDXL IDL FE ASIC CHN0 CHN15 Input Buffer ADC15 ADC0 D0 – D11 D0 – D11 FIFO CLK1:CLK0 2 Global bits (CLK1:CLK0)  00 or 11 : Control signals from internal logic  01: ADC control signals directly from FPGA

P1 ADC ASIC

Known issues for current ProtoDUNE ADC

• Non-linearity (NL)
• Stuck bits
• Some bits lost randomly in a wire

waveform e.g. 101,001 ⇒ 000,000 or 111,111

• Can be mitigated by identifying

them and interpolating the waveform

• Low temperature degrades the

electronics and read/write logics

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noise non-linearity stuck bit at 63 stuck bit at 0

Known issues for current ProtoDUNE ADC

• Non-linearity (NL)
• Stuck bits
• Some bits lost randomly in a wire

waveform e.g. 101,001 ⇒ 000,000 or 111,111

• Can be mitigated by identifying

them and interpolating the waveform

• External clock eases both issues
• NL is sensitive to clock settings

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Motivation of the NL calibration

• 600e- ENC (equivalent noise charge) at ProtoDUNE
• Given 14 mV/fC (preamp) and 0.3 mV/ADC conversion
• 600 e- ≈ 0.1 fC ≈ 1.4 mV ≈ 4.5 ADCs
• Would like to control the NL below 4 ADC for ADCtrue-ADCmeasure in the

useful range

By Hucheng

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Difficulty from a bench test to ProtoDUNE

• Bench test

11 WIRE SIGNAL

CALIBRATION SIGNAL (KNOWN VOLTAGE)

• ProtoDUNE

No direct voltage input!

Also, NL is sensitive to clock settings

• (bench test) clock is tuned for

each ADC

• (protoDUNE) one clock shared by

four ADC curcuits

Idea of the NL calibration setup

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• Similar setup as in MicroBooNE
• 6 bit pulser, i.e. 64 programmable amplitudes (<1.4V)
• four adjustable gains of preamplifier
• R(t): electronics response of preamplifier
• fNL: non-linearity from ADCtrue to ADCmeasure

Preamplifier 𝜊: gain R(t): response Pulser ηδ(t) ADC fNL: non-linearity V(t) A(t)

• C. Adams et al., Ionization Electron Signal Processing in Single Phase LArTPCs II.

Data/Simulation Comparison and Performance in MicroBooNE arXiv:1804.02583

Caveat: cold environment also changes the response

Effective sampling rate

• 0.5 μs sampling (2 MHz)
• shift t0 => effectively higher sampling rate

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Direct measurement of non-linearity?

• Given a precise prediction of the preamp response

 a direct measurement

• However, low temperature change the response significantly

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ADCmeasure ADCtrue A MC simulatoin

A(t) t

…

𝜃𝐻: 64*4 A(t) t × 1/ 𝜃𝐻 with NL

Naïve idea of the impact from NL

• Assuming pulse voltage

and the preamp gain do NOT change the shape

• f response
• NL distorts the shape

differently for high ADC and low ADC

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V(t) t

…

𝜃𝐻: 64*4 pulse voltage & preamp gain V(t) t × 1/ 𝜃𝐻 w/o NL

Sanity check with a MC simulation

w/o NL with NL All waveforms match perfectly

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ADCmeasure ADCtrue × 1/ 𝜃𝐻 Input NL in MC

Calibration strategy

• By assuming a function of non-linearity
• a piecewise function
• or a polynomial function
• Minimize the variance in A(t)/𝜃G
• i.e. the effective response function
• ~O(10k) data points & ~O(10) unknowns

 should be a solvable problem

• A channel by channel calibration plan

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NL varies among channels

ADCmeasure

Proof of principle with MC simulation

ΔV Pluse input

C (~185fF)

pin62 Chn_N

CSA SHAPER

Gain: 4.7, 7.8, 14, 25 mV/fC VDAC: 0 ~ 1.2V 63 steps

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Amp output saturation Amp input saturation Pulse voltage Preamp output voltage 9900 points 10 MHz effective sample rate

• By ignoring some saturations

in preamp, a 10k data set is possible

ADCmeasure / (VDAC × Gamp) ADCtrue

ADCmeasure

𝜓2(𝛽) = ෍

𝑗

𝐵𝑗 + 𝑔 𝛽 𝐵𝑗 − 𝑆 𝛽−1 𝑢𝑙 𝐻𝑗

2

𝜓2 minimization

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i-th data point NL correction function

(To be fitted out)

index of the 𝛽-th iteration 𝐻𝑗 = pulse voltage × preamp gain

(A normalization of charge input)

Time tick for 𝐵𝑗 𝑆 𝛽−1 (𝑢𝑙) =

1 𝑂 σ 𝐵𝑗+𝑔(𝛽−1)(𝐵𝑗) 𝐻𝑗

is the effective response function

(Calculated with the NL function from best fit

• f previous iteration)

(𝐵𝑗, 𝐻𝑗, 𝑢𝑙)

χ2 minimization (cont’)

𝑔 𝐵𝑗 = 𝑧0 + 𝑧1 − 𝑧0 1000 𝐵𝑗 − 0 , 𝐵𝑗 ∈ [0,1000) 𝑧1 + 𝑧2 − 𝑧1 1000 𝐵𝑗 − 1000 , 𝐵𝑗 ∈ [1000,2000) 𝑧2 + 𝑧3 − 𝑧2 1000 𝐵𝑗 − 2000 , 𝐵𝑗 ∈ [2000,3000) 𝑧3 + 𝑧4 − 𝑧3 1000 𝐵𝑗 − 3000 , 𝐵𝑗 ∈ [3000,4000) = 𝑐0𝑧0 + 𝑐1𝑧1 + 𝑐2𝑧2 + 𝑐3𝑧3 + 𝑐4𝑧4

= 𝑐0 = 1 −

𝐵𝑗 1000 , 𝑐1 = 𝐵𝑗 1000 , 𝐵𝑗 ∈ [0,1000)

𝑐1 = 1 − 𝐵𝑗−1000

1000 , 𝑐2 = 𝐵𝑗−1000 1000 , 𝐵𝑗 ∈ [1000,2000)

𝑐2 = 1 − 𝐵𝑗−2000

1000 , 𝑐3 = 𝐵𝑗−2000 1000 , 𝐵𝑗 ∈ [2000,3000)

𝑐3 = 1 − 𝐵𝑗−3000

1000 , 𝑐4 = 𝐵𝑗−3000 1000 , 𝐵𝑗 ∈ [3000,4000)

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For a piecewise function, the coefficients are calculated before the minimization

1000 2000 3000 4000 y1 y2 y3 y4 y5 𝐵𝑗 𝑔(𝐵𝑗)

bothers = 0

χ2 minimization (cont’)

• Given 𝑔 𝐵𝑗 from last iteration (𝛽-1 th) or initial guess (0-th), an

effective response function 𝑆(𝑢𝑙) is obtained e.g., 𝑔 𝐵𝑗 = 𝑐0𝑧0 + 𝑐1𝑧1 + ⋯ + 𝑐4𝑧4 (five points)  𝜓2 = σ 𝐵𝑗 + 𝑐0𝑧0 + ⋯ + 𝑐4𝑧4 − 𝑆(𝑢𝑙)𝐻𝑗 2 =

𝐵𝑗−𝑆𝐻𝑗 … 𝐵𝑛−𝑆𝐻𝑛 − −𝑐0

𝑗

… −𝑐1

𝑗

… −𝑐2

𝑗

… −𝑐3

𝑗

… −𝑐4

𝑗

… 𝑧0 𝑧1 𝑧2 𝑧3 𝑧4 2

= 𝑁 − 𝑆 ⋅ 𝑇 2 ⇒ By minimizing 𝜓2, {𝑧0, 𝑧1, 𝑧2, 𝑧3, 𝑧4} ≡ 𝑇 = 𝑆𝑈𝑆 −1𝑆𝑈𝑁 ⇒ Iterate the minimization until 𝑔 𝐵𝑗 converges

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Evolution of the “best-fit” 𝑔(𝐵𝑗) and 𝑆(𝑢)

• Given initial value {𝑧𝑗} = {0, 0, 0, 0, 0}
• After several times of iterations, “best-fit” NL 𝑔(𝐵𝑗) and effective

response 𝑆(𝑢) tends to be stable

• The spread in 𝑆(𝑢) significantly shrinks after minimization

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True

• Iter. #1
• Iter. #2

𝑆(𝑢)

True Initial

ADCtrue – ADCmeasure ADCmeasure

Electronics response bias ≈ 9 NL bias?

For initial values {𝑧𝑗} = {𝑧true}

• Not surprising. Ture 𝑔(𝐵𝑗) and 𝑆(𝑢) are obtained given the initial

values close to the true values

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𝜓2= 5E-5 (iter# 5)

For initial values {𝑧𝑗} = {-10, -10,-10,-10,-10}

• The spread in 𝑆 𝑢𝑙 is barely seen after iterations of 𝜓2 minimization
• Smaller biases in both 𝑔 𝐵𝑗 and 𝑆(𝑢𝑙) than {𝑧𝑗} ={0, 0, 0, 0, 0}
• Will the bias be a problem? (next slide)

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Δ=3.5

Initial

𝜓2= 0.0016 (iter# 5)

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time R(t)

• - “best fit” 1
• - “best fit” 2
• - true

Signal formation 𝐵𝑗 = 𝑆 ⋅ 𝐻𝑗 − 𝑔

𝑗 Electronics response Charge input NL effect

Signal processing 𝐻𝑗 = 𝐵𝑗 + 𝑔

𝑗 /𝑆 Signal measurement NL correction Electronics response deconvolution

Given a data set {𝐵𝑗, 𝐻𝑗}, and two “best-fits” 𝑔

𝑗

𝑆 = (𝐵𝑗 + 𝑔

𝑗)/𝐻𝑗

𝑔

𝑗 ′

𝑆′ = (𝐵𝑗 + 𝑔

𝑗 ′)/𝐻𝑗

𝑆′𝐻𝑗 − 𝑔

𝑗 ′

𝑆𝐻𝑗 − 𝑔

𝑗 ⇒

𝑩𝒋 ⇐ Similarly, for a signal 𝐵𝑗, two effective NL and response lead to same charge results For a charge 𝐻𝑗, Two “best-fit” NL and responses are equivalent for charge deconvolution!

MC validation of the degeneracy

• Given a same charge input,

the waveform predictions are close (<1 ADC) for

• Effective response and NL from

best-fit of {𝑧𝑗} = {0,0,0,0,0}

• True response and NL

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ADCmeasure Fitted response + fitted NL True response + true NL

NL bias in “best-fit” is not a problem!

NL correction

Interim summary

• Principle of ADC nonlinearity (NL) calibration for protoDUNE was

studied through a simplified Monte Carlo study (will improve it!)

• With a series of well controlled pulses to the charge preamplifier, an

effective ADC NL and an effective electronics response function of the preamplifier can be obtained

• The ionization charge can be accurately extracted given these two

effective response functions

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Working plan

• Carlos Sarasty from Cincinnati University join us this summer
• Towards a more realistic MC
• More realistic NL function (is minimization still available?)
• Induction plane waveform
• Pedestal
• Accuracy of preamplifier gain
• Impact of stuck bits
• Let’s work on real data!
• Bench test data taken by Shanshan Gao (BNL)
• Verify the algorithm

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Helpful discussion with DAQ group

• There are details to be worked out, but there is no show stopper
• Current difficulty in DAQ is that it takes 2 mins to change FE settings

and switch to a new run

• Take 4 preamp gains, 64 pulser voltages, and 5 time-zero shift in

calibration, it will take about 1.5 days in switching runs

• Two possible solutions:

a) Reduce the number of scan by studying the precision of calibration b) Develop a new DAQ software module that allows FE changes during a run

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