[PPT] - 4. MOS: Device Operation and Large Signal Model Lecture notes: PowerPoint Presentation

SLIDE 1

4. MOS: Device Operation and

Large Signal Model

Lecture notes: Sec. 4 Sedra & Smith (6th Ed): Sec. 5.1-5.3 Sedra & Smith (5th Ed): Sec. 4.1-4.3

ECE 65, Winter2013, F. Najmabadi

SLIDE 2

Operational Basis of a Field-Effect Transistor (1)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (2/29)

P-type semiconductor Insulator Metal Dopent ions Holes (majority carries)

Consider the hypothetical semiconductor below: (constructed similar to a parallel plate capacitor)

Electrical contact

SLIDE 3

Operational Basis of a Field-Effect Transistor (2)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (3/29)
If we apply a voltage v1 between electrodes, a

charge Q = C v1 will appear on each capacitor plate.

The electric field is strongest at the interface with the

insulator and charge likes to accumulate there.

Holes are pushed away from the insulator

interface forming a “depletion region”.

Depth of depletion region increases with v1.

Depletion Region (no majority carrier)

If we increase v1 above a threshold value (Vt),

the electric field is strong enough to “pull” free electrons to the insulator interface. As the holes are repelled in this region, a “channel” is formed which contains electrons in the conduction band (“inversion layer”).

Inversion layer is a “virtual” n-type material.

Depletion Region (no majority carrier)

Inversion layer (“channel”)

SLIDE 4

Operational Basis of a Field-Effect Transistor (3)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (4/29)

With inversion layer (v1 > Vt):

A current will flow in the channel
Current will be proportional to electron

charge in the channel or (v1 − Vt )

Magnitude of Current i2 is controlled by

voltage v1 (a Transistor!)

We apply a voltage across the p-type semiconductor:

(Assume current flows only in the n-type material, ignore current flowing in the p-type semiconductor)

No inversion layer (v1 < Vt):

No current will flow

SLIDE 5

Operational Basis of a Field-Effect Transistor (4)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (5/29)
We need to eliminate currents flowing in the p-type, i.e.,

current flows only in the “channel” which is a virtual n-type.

Body-source and body-drain junctions should always be in reverse bias for FET to work!
Make n-type material terminals (set up diodes between terminals & p-type “body”)
Heavy doping of the n-type terminals provides a source of free electrons for the channel.
Make insulator layer as thin as possible to increase the electric field.

SLIDE 6

Channel width (L) is the smallest feature on the chip surface

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (6/29)

MOSFET implementation on a chip MOSFET “cartoons” for deriving MOSFET characteristics MOSFET (or MOS): Metal-oxide field-effect transistor NMOS: n-channel enhancement MOS

SLIDE 7

NMOS i-v Characteristics (1)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (7/29)
To ensure that body-source and body-drain junctions are reversed bias, we

assume that Body and Source are connected to each other and vDS ≥ 0.

We will re-examine this assumption later
Without a channel, no current flows (“Cut-off”).
For vGS > Vtn, a channel is formed. The total

charge in the channel is ) SiO (for F/m 10 45 . 3 9 . 3 insulator

f

y permitivit : insulator

f

Thickness : area unit per e Capacitanc : ) (

2 11 −

× = = = = = = ε ε ε ε

x
x
x
x
x
x
x

tn GS

x

t t C L W C C

V

v WL C CV |Q|

Overdrive Voltage: VOV = vGS –Vtn

SLIDE 8

NMOS i-v Characteristics (2)

vGS > Vtn A channel is formed
Apply a small vDS between drain & source.
F. Najmabadi, ECE65, Winter 2013, Intro to MOS (8/29)
A current flows due to the “drift” of electrons

in the n-channel:

DS OV

x

n D DS tn GS

x

n D

v V L W C i v V v L W C i ) ( µ µ = − = For small vDS, MOS acts as a resistance with its conductivity controlled by VOV (or vGS). V L W C g v g i

OV

x

n DS DS DS D

with µ = =

SLIDE 9

NMOS i-v Characteristics (4)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (9/29)
When vDS is increased the channel becomes narrower

near the drain (local depth of the channel depends on the difference between VG and local voltage).

Triode Mode

[ ]

2

5 .

DS DS OV

x

n D

v v V L W C i − = µ

When vDS is increased further such that vDS = VOV ,

the channel depth becomes zero at the drain (Channel “pinched off”).

When vDS is increased further, vDS > VOV , the

location of channel pinch-off remains close to the drain and iD remains approximately constant.

Saturation Mode

2

5 .

OV

x

n D

V L W C i µ =

SLIDE 10

NMOS i-v Characteristics (5)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (10/29)

For a given vGS (or VOV)

SLIDE 11

NMOS i-v Characteristics Plot (1)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (11/29)
NMOS i-v characteristics is a surface

* Plot for Vt,n = 1 V and µnCox (W/L) = 2.0 mA/V2

) , (

DS GS D

v v f i =

SLIDE 12

NMOS i-v Characteristics Plot (2)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (12/29)

Looking at surface with vGS axis pointing out of the paper* *Note: surface was truncated (i.e., vGS < 5 V)

SLIDE 13

NMOS i-v Characteristics Plot (3)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (13/29)

SLIDE 14

Channel-Width Modulation

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (14/29)
The expression we derived for saturation region

assumed that the pinch-off point remains at the drain and thus iD remains constant.

In reality, the pinch-off point moves “slightly”

away from the drain: Channel-width Modulation

( )

A DS OV

x

n D

V v V L W C i / 1 1 5 .

2

= + = λ λ µ

SLIDE 15

Body Effect

Recall that Drain-Body and Source-Body diodes should be reversed biased.
We assumed that Source is connected to the body (vSB = 0) and vDS = vDB > 0
In a chip (same body for all NMOS), it is impossible to connect all sources

to the body (all NMOS sources are connected together.

Thus, the body (for NMOS) is connected to the largest negative voltage

(negative terminal of the power supply).

Doing so, changes the threshold voltage (called “Body Effect”)
F. Najmabadi, ECE65, Winter 2013, Intro to MOS (15/29)

( )

| 2 | | 2 |

, F SB F tn tn

V V V φ φ γ − + + =

In this course we will ignore body effect as well as other second-
rder effects such as velocity saturation.

SLIDE 16

P-channel Enhancement MOS (PMOS)

A PMOS can be constructed analogous to an NMOS: (n-type body), heavily

doped p-type source and drain.

A virtual “p-type” channel is formed in a P-MOS (holes are carriers in the

channel) by applying a negative vGS.

i-v characteristic equations of a PMOS is similar to the NMOS with the

exception:

Voltages are negative (we switch the terminals to have positive voltages: use

vSG instead of vGS ).

Use mobility of holes, µp , instead of µn in the expression for iD
F. Najmabadi, ECE65, Winter 2013, Intro to MOS (16/29)

SLIDE 17

MOS Circuit symbols and conventions

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (17/29)

PMOS NMOS

SLIDE 18

MOS i-v Characteristics Equations

NMOS (VOV = vGS – Vtn)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (18/29)

[ ]

DS OV

x

n D OV DS OV DS DS OV

x

n D OV DS OV D OV

v V L W C i V v V v v V L W C i V v V i V λ µ µ + = ≥ ≥ − = ≤ ≥ = ≤ 1 5 . and : Saturation 2 5 . and : Triode : Off

Cut

2 2

PMOS (VOV = vSG – |Vtp|)*

[ ]

SD OV

x

p D OV SD OV SD SD OV

x

p D OV SD OV D OV

v V L W C i V v V v v V L W C i V v V i V λ µ µ + = ≥ ≥ − = ≤ ≥ = ≤ 1 5 . and : Saturation 2 5 . and : Triode : Off

Cut

2 2

*Note: S&S defines |VOV |= vSG – |Vtp| and uses |VOV |in the PMOS formulas.

SLIDE 19

MOS operation is “Conceptually” similar to a BJT -- iD & vDS are controlled by vGS

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (19/29)

Controller part: Circuit connected to GS sets vGS (or VOV ) Controlled part: iD & vDS are set by transistor state (&

utside circuit)
A similar solution method to BJT:
Write down GS-KVL and DS-KVL, assume MOS is in a particular state, solve

with the corresponding MOS equation and validate the assumption.

MOS circuits are simpler to solve because iG = 0 !
However, we get a quadratic equation to solve if MOS in triode (check MOS in

saturation first!)

SLIDE 20

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (20/29)

Example 1: In the circuit below, RD = 1 k, and VDD = 12 V. Compute vo for vi = 0, 6, and 12 V. (µnCox (W/L) = 0.5 mA/V2 , Vt = 2 V, and λ = 0 )

DS D DS D D DD GS i

v i v i R V v v + = + = = = 10 12 : KVL

DS

: KVL

GS

3

V 12 10 12 : KVL

DS
ff
Cut

V 2 : KVL

GS

3

= = → + × = = → → = < = =

DS

DS

D t GS i

v v v i V v v correct Assumption V 4 V . 8 V . 8 10 4 10 12 : KVL

DS

mA . 4 4 10 5 . 5 . 5 . V 4 : Saturation Assume

3 3 2 3 2

→ = > = = = → + × × = = × × × = = = ≥

− − OV DS DS

DS

OV

x

n D OV DS

V v v v v V L W C i V v µ

Part 1: vi = 0

V 4

ff
Cut

in Not V 2 6 : KVL GS = − = → = > = = −

t GS OV t GS i

V v V V v v

Part 2: vi = 6 V

DS

v v =

SLIDE 21

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (21/29)

Example 1: In the circuit below, RD = 1 k, and VDD = 12 V. Compute vo for vi = 0, 6, and 12 V. (µnCox (W/L) = 0.5 mA/V2 , Vt = 2 V, and λ = 0 )

DS D DS D D DD GS i

v i v i R V v v + = + = = = 10 12 : KVL

DS

: KVL

GS

3

incorrect Assumption V 10 V 13 V . 13 10 . 25 10 12 : KVL

DS

mA . 25 10 10 5 . 5 . 5 . V 10 : Saturation Assume

3 3 2 3 2

→ = > − = − = → + × × = = × × × = = = ≥

− − OV DS DS DS OV

x

n D OV DS

V v v v V L W C i V v µ V 10

ff
Cut

in Not V 2 12 : KVL

GS

= − = → = > = =

t GS OV t GS i

V v V V v v

Part 3: vi = 12 V

DS

v v =

SLIDE 22

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (22/29)

Example 1: In the circuit below, RD = 1 k, and VDD = 12 V. Compute vo for vi = 0, 6, and 12 V. (µnCox (W/L) = 0.5 mA/V2 , Vt = 2 V, and λ = 0 )

DS D DS D D DD GS i

v i v i R V v v + = + = = = 10 12 : KVL

DS

: KVL

GS

3

DS

v v =

[ ]

48 24 ] 20 [ 10 5 . 5 . 10 12 10 12 : KVL

DS

2 5 . V 10 : Triode Assume

2 2 3

3

3 2

= + − + − × × × × = + × = − = = <

DS DS DS DS DS DS D DS DS OV

x

n D OV DS

v v v v v v i v v V L W C i V v µ V 10 = − =

t GS OV

V v V

Part 3 (cont’d): vi = 12 V

mA 8 . 9 10 12 V 10 V 2 . 2 ) (incorrect 10 V 8 . 21

3

= → + × = = < = = = > = =

D DS D OV DS

OV

DS

i

v i V v v V v v

SLIDE 23

NMOS Transfer Function (1)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (23/29)

vi can be applied directly to MOS There is no need for a RG . Circuit Equations:

vGS = vi
NMOS iv characteristics: iD = f (vGS , vDS )
KVL:

vo = vDS = VDD − RD iD

SLIDE 24

NMOS Transfer Function (2)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (24/29)

2) Just to the right of point A:

VOV = vGS − Vt is small, so iD

is small.

vDS = VDD − RD iD is close to VDD
Thus, vDS > VOV and NMOS is in

saturation. 1) For vGS < Vt , NMOS is in cutoff: iD = 0 & vDS = VDD − RD iD = VDD

SLIDE 25

NMOS Transfer Function (2)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (25/29)

3) As vGS increases:

VOV = vGS − Vt and iD become larger;
vDS = VDD − RD iD becomes smaller.
At point B, vDS = VOV

4) To the right of point B, vDS < VOV = vGS − Vt and NMOS enters triode. Point B is called the “Edge of Saturation”

SLIDE 26

NMOS Transfer Function (2)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (26/29)

2) Just to the right of point A:

VOV = vGS − Vt is small, so iD

is small.

vDS = VDD − RD iD is close to VDD
Thus, vDS > VOV and NMOS is in

saturation.

3) As vGS increases:

VOV = vGS − Vt and iD become larger;
vDS = VDD − RD iD becomes smaller.
At point B, vDS = VOV

1) For vGS < Vt , NMOS is in cutoff: iD = 0 & vDS = VDD − RD iD = VDD 4) To the right of point B, vDS < VOV = vGS − Vt and NMOS enters triode. Point B is called the “Edge of Saturation”

SLIDE 27

Graphical analysis of NMOS Transfer Function (1)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (27/29)
KVL equation is a plane in this space.
Intersection of KVL plane with the iv

characteristics surface is a line.

NMOS operating point is on this line

(depending on the value of vGS.)

DS D D DD DS GS D

v i R V v v f i i-v + = = : KVL ) , ( : sitics Characteri NMOS

If we look from the bottom (iD

axis out of the paper), we can see the transfer function.

SLIDE 28

Graphical analysis of NMOS Transfer Function (2)

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (28/29)
Every point on the load line

corresponds to a specific vGS value.

As vGS increases, NMOS

moves “up” the load line.

Looking from the bottom Looking parallel to vGS axis

SLIDE 29

NMOS Functional circuits

F. Najmabadi, ECE65, Winter 2013, Intro to MOS (29/29)
Similar to a BJTs in the active mode,

NMOS behaves rather “linearly” in the saturation region (we discuss NMOS amplifiers later)

Transition from cut-off to triode can

be used to build NMOS switch circuits.

Voltage at point C (see graph)

depends on NMOS parameters and the circuit (in BJT vo = Vsat)!

We can also built NMOS logic gate